One likely sequence of machine instructions for a regular, orthogonal, 3-address RISC CPU would go something like this:
LOAD_MEMORY &a -> register01
LOAD_MEMORY &b -> register02
INT_ADD register01, register02 -> register01
LOAD_CONSTANT 1 -> register02
BIT_SHIFT register01, register02 -> register01
STORE_MEMORY &i, register01
Also, if a
is a local variable and the compiler can prove that it won't be accessed after this, it might put i
and a
at the same memory address.
For a CISC CPU with a more complex irregular instruction set, there might be shift instructions that work on memory, and take constants, and add instructions that work on memory, then it would look something like this:
INT_ADD_MEM &a, &b -> &i
BIT_SHIFT_MEM_CONSTANT &i, 1 -> &i
Again, a
and i
may have the same address, if a
is local and unused afterward.