Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [zynq]

Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.

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VHDL rising_edge on 1Hz GPS input

The FPGA project I am working on requires events within an FPGA to be triggered off a 1Hz PPS coming from a GPS module. I have sampled this pps and then tried implemented logic triggered by this sampled pps in the two processes below. This SO…
zoulzubazz
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Is it possible to use basic networking on an FPGA without an OS?

I need to set up networking (just a basic echo server) on an FPGA board (ZYNQ Ultrascale+) using only the PL side. The end goal is to DSP a large amount of data coming from a receiver through ethernet. I am aware that you can use LWIP on the PS…
AslanT
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How do you design a bare-metal Zynq PS-PL system with an accelerator/coprocessor in the PL?

I am new to FPGA development and am trying to build a simple system using the Zynq SoC (on the Zedboard). It will consist of an IP block generated using Vivado HLS which will accept arrays of data, operate on them, and produce result arrays. A…
user3482357
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gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where everything else is loaded into external…
pr871
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Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say that the board runs very hot and they should have…
N.E.C.
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FPGA Interrupt in FreeRTOS

I am using freeRTOS in Zedboard. I am able to enable the PL-PS interrupt in bare-metal program. I couldn't really find any documentation/tutorial on how to link the FreeRTOS and the PL interrupt system. I am currently migrating my software to…
user9870
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External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. Is there an input on the Arty Z7 board that…
jamie
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Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "Xmyip_LookupConfig", "Xmyip_CfgInitialize" etc…
user3219492
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Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and the IOB on the right represents the Zynq board…
pr871
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Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as such introduces skew of at least 500ps between the…
Thomas
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1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?

I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip. Is it possible to use single 8Gb chip for this IC?
Danesh_sa
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How to map custom IP to the output pin on FPGA

I have a custom IP created with 2 output pin (en1_out and dir1_out) May I know how to map these two pin to the PMod pin on FPGA (pin Y11 and pin AA11)? I have tried to open the elaborate design and in the I/O Ports I can't find these two pin. I am…
user9870
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How to encrypt Bitstream on RedPitaya board?

I have developed my own bitstream for the RedPitaya SDRlab 122-16. I wonder if it is possible to encrypt the bitstream. I already know that I need to set a .bin file including the software counterpart as the system is Zynq-based and I have…
Andreas80
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Why is retimer circuit provided for HDMI TX lines?

I am exploring a Zynq ultrascale+MPSoC design. While looking at the reference design of XCZU9FFVB1156 SOC evaluation board, in the HDMI interface there is a retimer IC in the transmitter side of Bank 128, which converts the HDMI signal to TMDS along…
BalkisMM
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How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than 32 KB, thus can fit into the L1 data cache. I…
EquipDev
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