Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

8 questions
16
votes
2 answers

Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm using as Video RAM for a VGA module): module text_ram #( parameter A = 10, …
Hugo Sereno Ferreira
  • 554
  • 1
  • 3
  • 20
2
votes
0 answers

What is Warning: Replacing memory \MEM with list of registers?

I have this little code that displays a binary count on LEDs: module main ( input clk, output [7:0] LED ); reg [7:0] MEM [0:'hffff]; reg [7:0] tx_byte; reg [31:0] cta = 0; assign LED = ~cta[31:24]; always @ (posedge…
Candid Moe
  • 209
  • 2
  • 9
1
vote
1 answer

nextpnr unconstrained error

I am trying to build a clock divide chain on an iCE40 UPduino card and have run into a problem with nextpnr. I've minimized a working / non-working example. This code works: // constraints file as follows: // set_io -nowarn clkin 20 #…
Bob_at_DPI
  • 11
  • 2
1
vote
1 answer

Why does yosys mark used sub-modules as unused?

Question: Why does yosys mark used sub-modules as unused? Background: I am trying to find a rough estimate of the area of a circuit. Some years ago, during my bachelor's, I have used a synthesis tool. IIRC, it was Synopsys. I don't have access to it…
Daniel Carvalho
  • 133
  • 5
1
vote
1 answer

SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive that I can use in my code that would prevent…
norandomtechie
  • 11
  • 1
1
vote
2 answers

ice40-hx8k: Weird input pin behaviour regarding digital HI voltage level

I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing: When I use a certain pin as output, the voltage level for a…
Katharina
  • 125
  • 1
  • 9
0
votes
1 answer

Synthesizing designs in yosys

If you have a sequential circuit in verilog or system verilog and want to synthesize it to specific gate types and flip-flops, how do you go about it. For example, may be synthesize the design to nor, and, or, nand, not etc. and flip-flops to use…
r360
  • 19
  • 1
-1
votes
1 answer

Support for ICE40UP5K-SG48I in IceStorm?

I hope this is the correct place for IceStorm questions .. The IceStorm website shows support for, iCE40-UP5K-UWG30 The Single Wire Aggregation Demo / Development Board from Lattice uses a Different part (package diff only?), ICE40UP5K-SG48I Will…
TomP
  • 1