The Vitis™ unified software platform is a new tool introduced in 2019, that combines all aspects of Xilinx® software development into one unified environment.
Questions tagged [xilinx-vitis]
1 questions
1
vote
0 answers
VHDL conversion between signed and float
I've a small IP core module which performs some operations on a float input. The module has been developed using vivado hls. As shown below, the float input of the module is taken as a std_logic_vector.
entity basic_test is
port (
ap_local_block…
Tony
- 11
- 2