Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

A popular manufacturer of FPGAs (Field Programmable Gate Arrays)—such as Spartan and Virtex—and CPLDs (Complex Programmable Logic Devices), including 9500XL and CoolRunner.

Xilinx homepage

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How to choose an FPGA?

I need to do digital signal processing on 8 analog lines at 10 kHz. This is quite a demanding task, and I was thinking that an FPGA might be the right approach. I am currently looking at dev kits from Xilinx, and since I have no experience with…
fpganewbie
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List of Xilinx file suffixes (for ISE)

I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead Some of the information they have provide is the…
Brian Carlton
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Project to learn VHDL

I am an EE student and can write [at least simple] programs in more languages than I have fingers. I have just started learning VHDL and I was wondering what a good project would be to really get to know the language and the relevant tools? I am…
jeremy
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FPGA firmware design: How big is too big?

I have a particularly large signal processing transform that needs to be ported from matlab to VHDL. It definitely requires some kind of resource sharing. A bit of calculation gave me the following: 512 ffts of 64-points 41210 multiply-add…
stanri
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Using SVN with Xilinx Vivado?

I just stated using Vivado in a new project and would like to put the project files under SVN. Vivado seems to create all the project files under the project name (say proj1): //proj1/ proj1.xpr …
FarhadA
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How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, however at the moment it will no longer fit in the…
Marcus10110
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Can I use differential I/O pins of FPGA as high speed comparator?

High speed comparators are rather expensive and speed is what FPGAs are very good at. On the other hand, FPGAs (in my case: XC3S400) have paired differential pins in each bank that their voltages are compared ( At least I think so !). They also…
Aug
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FPGA, first steps

Well this is a continuation of my question on FPGA over here. I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount of work with micro-controllers. I spent the last…
Kevin Boyd
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Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare situations, why do FPGA's have latches at all ? I…
nurabha
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What is a "half latch" in an FPGA?

In a paper about radiation hard FPGAs I came across this sentence: "Another concern regarding Virtex devices is half latches. Half latches are sometimes used within these devices for internal constants, as this is more efficient than using…
andrsmllr
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FPGA: count up or count down?

I am learning to use an FPGA (Papilio development board,which has a xilinx spartan3e, using vhdl). I need to divide an incoming pulse by a (hard coded) number. I can see 3 options - roughly, as pseudocode (using 10 counts as an example): Initialize…
AMADANON Inc.
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Simulating a simple test bench with a synthesized ROM core

I'm completely new to the world of FPGA's and thought I'd start with a very simple project: a 4-bit 7-segment decoder. The first version I wrote purely in VHDL (it's basically a single combinatorial select, no clocks necessary) and it seems to work,…
Cactus
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Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design clock) can be implemented on my Artix-7 200T. If I…
Paebbels
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Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example demonstrates this by a "ring-counter" which just…
Martin Zabel
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How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (Behavioural simulation) but does not synthesize…
ironstein
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