VUnit is an open source unit testing framework for VHDL/SystemVerilog designs. It features the functionality needed to realize continuous and automated testing of your HDL code.
Questions tagged [vunit]
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What kind of VHDL process is this?
This is from an example that comes with VUnit inside the array_axis_vcs fifo.vhd file.
PslChecks : block is
constant dx : std_logic_vector(d'left downto 0) := (others => 'X');
constant du : std_logic_vector(d'left downto 0) := (others =>…
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