Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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Why would an AND gate need six transistors?

I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense until one of my classmates told me he could…
Dev-XYS
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Why aren't fully asynchronous circuits more prevalent?

From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed. However, in today's market, speed in consumer products is one of the…
Corsair64
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Are chicken bits left in space-qualified ICs?

A chicken bit "is a bit on a chip that can be used by the designer to disable one of the features of the chip if it proves faulty or negatively impacts performance." Would space-qualified logic components leave this feature in, or would the final…
My Other Head
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Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM process while manufacturing SDRAM? What differences…
pjc50
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What method do you suggest for prototyping asynchronous circuits?

I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits. I keep searching using google and other means to find a good method to design VLSI asynchronous…
Dr. Ehsan Ali
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Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. For example: x = #10 y; will be considered as x =…
Anand
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What determines the maximum clock rate for a CPU?

What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range. All things being equal, if the 6502 is manufactured using the same materials,…
user148298
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How do the VLSI design rules for finFET differ from traditional MOSFET/CMOS design?

I'm taking an intro to VLSI class right now and we're learning the design rules for laying out chips on a 600 nm process. This was the state of the art in the early 90's so it should be a little out of date. From what I can tell, most modern…
Kip M.
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Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by the clock divider to get two other clocks:…
Mitu Raj
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Getting starting designing CMOS ASIC - What is the must have software?

What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would be nice.
Anon21
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Processor design: turning blocks on/off dynamically to save power?

I was wondering if this is possible and if it is done in current designs. Seemed like an interesting enough idea to me. Here's a little diagram I made to help try and explain: So let's say I'm clever and I build a bit of hardware that tracks the…
JDS
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Can a NOT gate be used to achieve 180 degree phase shift?

I have seen from various sources which say that a NOT gate cannot be used to achieve an 180-degree phase shift. Is this claim true? Edit: The question is definitely sounding unclear because that is how it was worded, but one thing I missed was it…
vineel13
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Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good reasons for this bias in the industry?
Revanth Kamaraj
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Ripple counters versus synchronous--pros, cons, and power consumption

Substantial edit--note that David Kessner's answer was written in response to the original posting; view the edit history to see what he was responding to From what I've read of digital design, there is a very strong tendency toward the use of…
supercat
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Implementation of AES algorithm using Systolic architecture

I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways : Systolic for Key expansion Systolic in MixColumn Systolic for the on-the-fly calculation of…
Amruta
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