Questions tagged [vivado-hls]
11 questions
1
vote
0 answers
VHDL conversion between signed and float
I've a small IP core module which performs some operations on a float input. The module has been developed using vivado hls. As shown below, the float input of the module is taken as a std_logic_vector.
entity basic_test is
port (
ap_local_block…
Tony
- 11
- 2
0
votes
0 answers
How do I use conditional compilation in Xilinx Vivado?
I want to conditionally include one of three files if the respective macro for that file has been defined. Normally I would define the macros in a separate file, say defines.v, and then include that in the top module.
The top module file would look…
Killjoy
- 91
- 7
0
votes
0 answers
How to map function arguments to a BRAM in HLS?
I try to implement an FPGA submodule from C through Vivado HLS.
My C function header is as follow:
My_function(int *data_A_in, int *data_B_in, int size_in, int *data_out, int size_out)
Is it possible to make HLS to map my pointers to a memory of the…
dsp_curious
- 25
- 5
0
votes
0 answers
Why is fread in Vitis HLS reading a bitmap file wrong?
I have a test bench for a Sobel filter in Vitis HLS. This test bench is reading an image via
if(Bitmap_Reader_Open("Test.bmp", &Width, &Height, &Bits) == -1)
{
printf("Can not open input image!\n\r");
return -1;
}
int…
Kampi
- 410
- 3
- 11
0
votes
1 answer
vivado HLS or SDsoc for use openCV
I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to solve the problem through parallel processing. What…
tom
- 1
0
votes
1 answer
HLS like programming on Actel devices
I have been using Xilinx FPGA devices for a while and I use HLS extensively to create parts of my design.
I have currently switched to Actel FPGA devices and specifically the ProASIC3 family, and wanted a similar functionality like HLS (Embedded C…
abunickabhi
- 354
- 3
- 17
0
votes
2 answers
AXI Stream write and read not synchronized
Searching "hls axi dma" on this site gives a few related issues but none of which I can use to fully deduct a solution for my problem.
My code generates "random" output on IO1 and reads input on IO4.
To test my code, I short IO1 and IO4 and, I keep…
niCk cAMel
- 127
- 6
0
votes
0 answers
How to crop/resize images in video stream on frame grabber with FPGA?
I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 FPGA and comes with this Custom Logic design kit…
jaduuuui
- 171
- 1
- 5
0
votes
0 answers
HLS: Unrolling the loop manually and function latency constraints
I have a TOP-level function of the following structure:
struct TYPE1 {uint8 ch[16];};
struct TYPE2 {uint8 ch[100];};
void FUNCT(hls::stream &inStream, hls::stream &outStream){
#pragma HLS INTERFACE axis port=inStream
#pragma HLS…
Nazar
- 3,142
- 4
- 35
- 62
0
votes
1 answer
Const type array in Vivado HLS
Could someone explain how HLS treats arrays that are declared constants? I declare an array as:
const uint8 myArray [100][100] = {....};
and then access the array by element in the loop. According to the UG902 on p.328, such array is implemented as…
Nazar
- 3,142
- 4
- 35
- 62
-2
votes
1 answer
Implement glDrawArrays function in FPGA
I need to implement glDrawArrays function in FPGA.
I understand it's part of the OpenGL library.
I'm trying to get to its source code to figure out what it contains.
Does anyone know of a tool that can convert functions from OpenGL to RTL?
ohad
- 1