Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

The Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

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279 questions

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1 answer

Is the initial block in Verilog sythesizable?

I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-synthesizable Verilog constructs (from the book Digital Logic Design Using Verilog by…

asked Jul 11 '18 at 13:02

Sandeep I

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1 answer

What is the difference between an array and a bus in Verilog?

I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following? What is the difference between an array and a bus? During declaration, a bus would look something…

fpga verilog vivado

asked Mar 12 '16 at 06:19

Caleb Reister

1,301
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27

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2 answers

How do I build and use my own VHDL library?

I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a standard library.(or similar) example: library…

vhdl library vivado activehdl aldec

asked Mar 27 '15 at 21:21

Hayden DeBoer

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1 answer

Vivado constraints wizard suggests a lot of nonsense generated clocks

I'm trying to apply timing analysis to a RISC-V MCU I have designed in SystemVerilog, in Vivado, for a Basys 3 board. My design contains several generated clocks, which are made by dividing the system clock (100MHz) by a number. I use fabric to do…

fpga verilog clock vivado timing-analysis

asked Oct 11 '22 at 13:28

Martel

1,213
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20

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Extremely long net in Xilinx synthesized design labeled "async_path". What's it for?

I used Vivado to synthesize a small design for the Xilinx xc7k-160t-1. The design includes a fifo instantiated with Vivado's XPM macros which crosses clock domains from 100.8MHz to 200MHz. When I opened the synthesized design, I saw these extremely…

fpga xilinx vivado

asked Oct 10 '22 at 15:14

John M

1,358
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26

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2 answers

systemverilog structure initialization with default = '1

Can someone shed light on what this SystemVerilog code should do: typedef struct { logic [15:0] a; logic [15:0] b; logic [15:0] c; } my_struct; localparam my_struct s = '{default:'1, c:0}; Is this legal? I can't quite figure out the spec well…

hdl system-verilog vivado

asked Jul 07 '15 at 20:50

nachum

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2 answers

FPGA logic threshold - distinguishing a logic 0 and 1

I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function generator giving a square wave that toggles between 0…

digital-logic fpga xilinx vivado artix-series-fpga

asked Oct 10 '22 at 23:42

PrematureCorn

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0 answers

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for this should be in my XDC file. For the above…

digital-logic fpga xilinx timing vivado

asked Jul 17 '18 at 10:42

chasep255

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2 answers

System Verilog generic modules and unused ports

I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like full, empty, almostFull and almostEmpty. However sometimes not all of the output signals are used,…

system-verilog vivado

asked Nov 07 '15 at 22:54

ted

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1 answer

BASYS3 FPGA pin planning and configuration question

I have designed a basic 8-bit CPU that is mapped onto FPGA fabric on a Digilent BASYS3 development board. The DRC results in a few error messages that I do not understand, with one of them being shown in the image below: Now I have found where I…

fpga pins vivado configuration

asked Feb 04 '23 at 22:33

David777

1,548
12
29

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2 answers

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the same design twice ( given the same software version ) ?

fpga vivado quartus

asked May 01 '19 at 16:44

shaiko

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1 answer

SATA controller on Artix 7

Problem background: My ultimate aim is to implement a SATA host controller on an Artix 7 FPGA. Having said that I am first focusing on the physical layer. Through my research I have found and read through open source IP located here:…

fpga vivado sata

asked Mar 01 '17 at 15:30

sacco

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1 answer

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 bytes and it happens 4 times. My MM2S (Memory…

fpga xilinx dma vivado

asked Jun 30 '15 at 15:51

João Pereira

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1 answer

32 Bit FileRegister with ALU

Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable. It should be like figure1 below. I'm taking inputs from named data input which has parsed as 2-4-4-4. First 2 bits are…

verilog system-verilog vivado alu register-file

asked May 28 '23 at 11:38

Jekolaw

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1 answer

What are the multiple drivers in this code?

Code: module controller_module(st_rst, clk, mem_rst,dis_rst, pe_rst, two_rst, three_rst, count, state ,two_end, s_end_1, s_end_2 , s_end_3, s_end_4, s3_end_22, s3_end_21, s3_end_12 ,s3_end_11, en_dis, input_11, input_12,…

digital-logic verilog system-verilog vivado

asked May 26 '23 at 14:55

P.F.

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