Questions tagged [virtuoso]

21 questions
4
votes
1 answer

6T SRAM cell write operation not working as expected in virtuoso

I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and I want to write 0 and 1 in cell after 10n…
Sparsh
  • 168
  • 8
2
votes
0 answers

Cadence Virtuoso CMOS layout: MIMcap become unrecognised after instantiating a new component

I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBLs. Component A has a large MIMcap (multiplier 60) with a…
Nitrogen
  • 21
  • 2
1
vote
1 answer

What is the meaning of a negative capacitance? - Cadence Virtuoso

What is the meaning of a negative capacitance in cadence virtuoso? Here in the following image, I just want to find the capacitance of transistors using "print-->DC operating point". Can you please justify the negative value of capacitance? For…
mohammad rezza
  • 442
  • 1
  • 11
1
vote
1 answer

What is the meaning of "a" and "z" in capacitor value - Cadence Virtuoso

What is the meaning of "a" and "z" in capacitor value? Here is the image: I think "a" is angstrom, But I am not sure about it.
mohammad rezza
  • 442
  • 1
  • 11
1
vote
0 answers

How can I find critical field in tsmc65 transistor parameter?

How can I find critical field in tsmc65 transistor parameters? Critical field is the field which electron velocity in transistor go into the saturation region.
1
vote
0 answers

How to find (mobility*Cox) and Vth

How to find "mobility*Cox" and "threshold voltage" of NMOS in cadence virtuoso? I have performed DC analysis in schematic environment and using NMOS model parameters, I tried to find mobility, Cox and threshold voltage. But I could not find them.…
mohammad rezza
  • 442
  • 1
  • 11
1
vote
1 answer

Allowed amount of input wreal data type at verilog-ams

I'm a newbie at using Verilog-ams and also I want to write a module for flash ADC for a specific application. I need to confine my voltages reference so I wrote this Verilog-ams code for testing input allowed value at wreal data type. I arranged a…
1
vote
1 answer

I want to implement this active inductor design in my circuit

I'm trying to use an active inductor instead of the inductor in my class e power amplifier, however, I'm having difficulties in getting the required values for the parameters, Cds, Cgs, Cgd, and Ceq, for example. I have the SPICE model for the…
CruderSein
  • 11
  • 1
1
vote
0 answers

How to add NCSU FreePDK45 to Cadence Virtuoso Library?

I'm looking for a comprehensive guide on how to add FreePDK45 to Cadence Virtuoso Library (2015 version). The installation guides included are not clear for first timers, and other resources available online are about installing other PDKs that…
eln05
  • 11
  • 1
0
votes
0 answers

The following branches form a loop of rigid branches (shorts) when added to the circuit in Cadence Virtuoso

I'm trying to build a Full Adder in Cadence Virtuoso using 2inp NAND Gate symbol. But I'm getting the following error, This is the circuit, Schematic of the symbol, What is the mistake and the solution??
0
votes
2 answers

All the currents and voltages are shown zero in my circuit - Cadence Virtuoso

In the following circuit, I do not know why all the currents and voltages are shown zero? My simulation just contains the "DC" simulation. After performing DC simulation, all the node voltages are zero and specially the nodes connecting to the…
mohammad rezza
  • 442
  • 1
  • 11
0
votes
0 answers

Cadence Virtuoso error: Expression evaluation failed

How can I solve this error in Cadence Virtuoso calculator? expression evaluation failed: waveVsWave(?x IDC("/V1/PLUS") ?y OP("/M0","ron")) I just want to show the output resistance versus drain current when drain-source voltage is constant.
mohammad rezza
  • 442
  • 1
  • 11
0
votes
0 answers

How can I plot "Vdsat" VS "Vgs" in Cadence Virtuoso?

How can I plot "Vdsat" VS "Vgs" in Cadence Virtuoso? I can place a voltage supply at the Vgs (gate-source voltage), then I give to its value a variable. After that, I can define that variable in the "ADE L". My problem is that I don't know how can I…
mohammad rezza
  • 442
  • 1
  • 11
0
votes
1 answer

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso?

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso? They are all abbreviated and there is not any guide there. For example, I want to know the value of "process transconductance parameter" or "kn". in…
mohammad rezza
  • 442
  • 1
  • 11
0
votes
1 answer

What is the meaning of "Unit Size NMOS (W=5*325nm/L=5*65nm)"

What is the meaning of the following sentence: Simulate a Unit Size NMOS (W=5 * 325nm/L=5 * 65nm) and PMOS (W=5325nm/L=565nm) with in CMOS technology. Well, this transistor is a MOSFET with 65nm feature size. The multiplier "5*", is vague for me.…
mohammad rezza
  • 442
  • 1
  • 11
1
2