Highest Voted 'virtex-series-fpga' Questions - Electrical Engineering Stack Exchange

7

votes

1 answer

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and how do we verify this.

asked May 31 '19 at 06:10

srihari

71
3

6

votes

1 answer

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) Serial-ATA Gen1, Gen2 and Gen3, especially…

fpga vhdl xilinx sata virtex-series-fpga

asked Aug 15 '14 at 06:17

Paebbels

3,897
2
18
43

3

votes

1 answer

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would like to fill the entire DDR memory module with…

fpga memory xilinx virtex-series-fpga

asked Dec 08 '14 at 20:56

Arash Fotouhi

203
4
9

2

votes

0 answers

How to determine number of pixels required to interface any vga display

I have a guide that tells me that for interfacing 640x480 screen you need 800 pixels in a row and 521 lines along with all of that front and back porch stuff I wanna know how do they determine that number? If i have a screen of different resolution…

fpga xilinx hdl vga virtex-series-fpga

asked Jul 31 '16 at 06:01

Ishmeet Bindra

31
3

2

votes

2 answers

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 bit for SRLs. Why are SRLs restricted to 2^5…

fpga xilinx shift-register virtex-series-fpga

asked May 22 '15 at 02:39

Paebbels

3,897
2
18
43

2

votes

1 answer

Optimum aspect ratio for storing data in Block RAMs

I am working on Xilinx virtex 4 FPGA. I want to store some filter coefficients in Block RAMs. Specifically, I have many sets of filter, each set having 64 coefficient, each coefficient is of 18 bits. Each set has to be mapped on a distinct Block…

programming xilinx ram virtex-series-fpga

asked Jul 23 '14 at 05:56

KharoBangdo

165
1
6

1

vote

0 answers

Package delay to Mils conversion

I was able to calculate the package delay values in pico seconds by using the IBIS models from the xilinx site. For example: For a Virtex-5 FPGA IBIS model, the package ff323_5vlx20t_ibis.pkg is provided. Let us choose the pin B9. From Capacitance…

xilinx delay virtex-series-fpga

asked Sep 18 '20 at 12:36

MightyBeard007

197
2
18

1

vote

1 answer

VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

The following is the top level module of a VC707 based Microblaze/PS2 controller. I have connected a FMC-CE GPIO Daughter Card to the FMC1 Connector on the FPGA and a PMOD-PS2 on the 6 pin GPIO header on the board. What do I need to do to pass…

vivado virtex-series-fpga ps2 microblaze

asked Mar 04 '19 at 21:13

Vahe

171
1
11

1

vote

1 answer

How to interface UART with BRAM in xilinx virtex 5

I am trying to design a simple loop of communication system between pc and FPGA virtex 5, for this purpose I interfaced a BRAM with uart module, I am using VHDL as the hardware description language, the memory used is a 16 byte simple dual port…

fpga vhdl xilinx virtex-series-fpga

asked Sep 14 '16 at 11:38

Taki Eddine

11
3

1

vote

2 answers

Timing complexity for correlation implementation on FPGA

Let's say we have a database of five thousand 512 point discrete signals. Each database entry is unique in itself. The important point to note about the signals in the database is that out of the 512 points, more than half of the points are zero for…

fpga signal-processing virtex-series-fpga

asked Jul 26 '16 at 07:43

Deval Mehta

11
1

1

vote

1 answer

Instantiating and using ppc440 core in Virtex 5 FPGA

I am new to Virtex 5 which has an embedded PPC440 core in it (XC5VFX70T). I am using the Xilinx ML507 board for my design. I created the embedded core using XPS and instantiated it in my HDL project. As peripherals, I am using a DDR2 controller,…

virtex-series-fpga

asked Feb 04 '16 at 06:00

rvkrysh

156
1
10

1

vote

1 answer

Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device. During initialization, I am able to see COMRESET, COMINIT and COMWAKE from host and…

fpga xilinx sata virtex-series-fpga

asked Jan 19 '16 at 05:56

sunni

19
2

1

vote

1 answer

how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it indicating any kind of error? Please give any comment to…

xilinx synthesis rtl virtex-series-fpga

asked Jul 19 '15 at 11:07

Shine_flower

151
1
2
9

1

vote

1 answer

How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want to see whether it performing logically fine after…

fpga verilog virtex-series-fpga

asked May 14 '15 at 05:43

SW.

348
1
11
24

1

vote

1 answer

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know IOSTANDARD LVDS, but translate for Series7…

xilinx synthesis ise virtex-series-fpga ucf

asked Mar 17 '15 at 23:31

Paebbels

3,897
2
18
43

Questions tagged [virtex-series-fpga]