Questions tagged [vhdl-2008]
11 questions
7
votes
3 answers
VHDL rising_edge on 1Hz GPS input
The FPGA project I am working on requires events within an FPGA to be triggered off a 1Hz PPS coming from a GPS module. I have sampled this pps and then tried implemented logic triggered by this sampled pps in the two processes below.
This SO…
zoulzubazz
- 71
- 3
2
votes
1 answer
VHDL: How to use records as PORTS with IN and OUT parameters?
Is there a syntax where one can use a record type in a PORT declaration, but specify that certain members of the record are IN or OUT?
I could be asking an XY problem here; so the overall picture that I would like to create an entity that has a…
Alex Schultz
- 23
- 3
2
votes
1 answer
Resources for learning Open Source VHDL Verification Methodology (OSVVM)
I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following:
Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based simulations? If so, how pls (any tutorials…
Arvind Gupta
- 97
- 1
- 5
1
vote
1 answer
Signals acting weirdly in VHDL
I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example
if rising_edge(clk) then
but in this testbench, after the first wait statement and giving values Rst, Load, and Data,…
B.Adlane
- 45
- 3
1
vote
1 answer
Vivado cannot determine equality operator for enum type in assert statement
I have the following assertion in my code:
assert (debug_decoded_opcode = types.AUIPC_OP) report "00000317 not AUIPC";
Vivado gives the error:
ERROR: [VRFC 10-724] found '0' definitions of operator "=", cannot determine exact overloaded matching…
tuskiomi
- 585
- 6
- 23
0
votes
2 answers
How to minimize slack for mod in numerical package?
Here is the snippet of the code in VHDL.
I mean this IEEE.numeric_std.all
shift_reg <= b"0011" & std_logic_vector("/" (temp_result, divisor) (3 downto 0));
temp_result <= temp_result mod divisor;
divisor <= divisor / 4d"10";
This is what I got…
kile
- 273
- 8
0
votes
1 answer
Alternative to using FSM for implementing round robin
It is easy to implement round robin (A->B->C->A->B->C..) using FSM in VHDL. Is there an alternative to FSM? For some reason, I have a feeling there is a nice and neat implementation without using FSM.
user7586189
- 161
- 5
0
votes
1 answer
VHDL: How to assign a default value to a procedure parameter?
I have some existing code that is making use of a procedure for a bus functional model. I am going to add new functionality that will require me to add a new parameter into this procedure. I want, in order to keep the code backward compatible, the…
quantum231
- 11,218
- 24
- 99
- 192
0
votes
1 answer
Where are VHDL type cast functions defined?
In VHDL one can cast one type to another using the name of the other type e.g
signal x : std_logic_vector(7 downto 0);
signal y : signed(7 downto 0);
...
y <= signed(x)
Here we use the type as if it was name of a function. Where exactly are these…
quantum231
- 11,218
- 24
- 99
- 192
0
votes
1 answer
Does VHDL 2008 have built in function to convert std_logic_vector to character type?
What is the 'standard' way to convert an std_logic_vector value into character type? It seems that first I convert it to an integer and then to character using the ASCII table. However, I am not sure how to do this in code.
Also, what is the…
gyuunyuu
- 1,933
- 7
- 31
-1
votes
1 answer
VHDL statement meaning
Can someone explain to me what is the meaning of this statement in VHDL:
aIn : in STD_LOGIC;
signal oSyncStages : std_logic_vector(STAGES-1 downto 0);
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
Based on the response on this…
sharuhkhan
- 1
- 1