Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

VHDL is turned into logic through a process called synthesis.

Further reading

Wikipedia's article on VHDL
The Hamburg VHDL Archive
wikibook programmable logic/VHDL
Free model foundry - a collection of VHDL/Verilog models of existing chips.
Stack Overflow documentation for VHDL

1706 questions

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votes

11 answers

VHDL vs. Verilog

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?

vhdl verilog hdl

asked Jul 13 '11 at 08:00

stevenvh

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How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've heard a couple of people say ASIC design is very…

fpga vhdl verilog software asic

asked Mar 25 '12 at 08:07

Robin Rodricks

866
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7 answers

Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, but I'm specifically interested in stuff people have actually looked at and found…

microprocessor fpga softcore verilog vhdl

asked Mar 05 '10 at 16:08

Eli Bendersky

566
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7 answers

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

I built a mod-16 counter, and the output result is a INTEGER (all the examples I saw used INTEGER). I built a hex-to-7-segment-display decoder, and its input is a STD_LOGIC_VECTOR (wrote it that way because it was easy to map out the truth…

vhdl

asked Sep 21 '10 at 12:57

J. Polfer

3,780
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10 answers

Free IDE for VHDL and Verilog

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?

vhdl verilog ide

asked Dec 26 '11 at 11:37

itsaboutcode

507
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29

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4 answers

VHDL: Component vs Entity

I am wondering what is the difference between component an entity. I would like to know in which cases is better to use components instead of entities. Thank you so much.

vhdl components

asked Jul 12 '11 at 06:48

Peterstone

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17 answers

Most affordable FPGA dev kit for learning VHDL and FPGA theory?

I'm looking for something that I can play around with but not spend too much on. I'm not eligible for an academic discount so take that into account when making suggestions.

fpga vhdl

asked Oct 07 '10 at 15:05

Matthew Miano

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3

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4 answers

std_logic or std_ulogic?

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The alternative would be std_ulogic, which is not resolved. This surprises me because usually, you're not describing a bus,…

vhdl

asked Jul 28 '11 at 12:51

Philippe

1,412
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26

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4 answers

VHDL that can damage FPGA

I read somewhere that bad VHDL code can lead to FPGA damage. Is it even possible to damage a FPGA with VHDL code? What kind of conditions would cause this and what are the worst case scenarios?

fpga vhdl

asked Mar 21 '17 at 19:42

ESD

539
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25

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11 answers

VHDL interview question - detecting if a number can be divided by 5 without remainder

I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they don't want you to use mod or rem) and while I did…

vhdl state-machines

asked Dec 15 '17 at 19:42

nettek

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7 answers

How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented using hardwares. So I was wondering how should I go…

simulation vhdl verilog hdl

asked Jul 14 '10 at 16:53

Rick_2047

3,897
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4 answers

VHDL IDE for a GNU/linux environment

I have to study VHDL from 0 and i'd like to have an option that runs under a linux kernel instead of NT/Windows: any tips? I can also really appreciate some good links to good VHDL resources for a beginner, thanks.

vhdl ide

asked Nov 22 '11 at 06:08

Micro

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VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc. I use std_logic at top level ports, but internally I was using ranged integers all over the place. However, I've stumbled across a few references to…

vhdl synthesis

asked Mar 21 '11 at 05:37

darron

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Any native Mac OS X environments for getting started with VHDL / FPGAs?

The title pretty much sums up my question: Are there any native Mac OS X environments for getting started with VHDL / FPGAs?

fpga vhdl mac

asked Oct 22 '10 at 18:18

Kaelin Colclasure

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Soft-CPU verification

I'm currently in the process of designing a simple CPU in VHDL using Xilinx ISE and ISIM. The design portion is going remarkably well, but I can't seem to figure out a way to do verification in a consistent manner. Right now I have a VHDL test…

fpga vhdl cpu test

asked Sep 03 '12 at 19:33

drxzcl

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