Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

Verilog is turned into logic through a process called synthesis. When targeting synthesis (rather than testbench code or esoteric use cases), a sub-set of the full language features will be used since the language can express features which do not map directly to physical gates.

Verilog can be used for many applications, from FPGA implementations, to ASIC design. The application can have a profound impact on how Verilog can be used.

Sometimes it is referred to as Verilog HDL. However it is not the same as VHDL.

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VHDL vs. Verilog

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?
stevenvh
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Can an FPGA design be mostly (or completely) asynchronous?

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere. I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those clocks. Are they absolutely required, or can an…
Roman Starkov
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How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've heard a couple of people say ASIC design is very…
Robin Rodricks
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Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, but I'm specifically interested in stuff people have actually looked at and found…
Eli Bendersky
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Free IDE for VHDL and Verilog

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
itsaboutcode
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Why are inferred latches bad?

My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided. What exactly is wrong with inferred latches? They certainly make combinatorial…
Randomblue
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Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following: We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is…
Void Star
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How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented using hardwares. So I was wondering how should I go…
Rick_2047
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What is the "+:" operator called in Verilog?

I am going through a Verilog test case, and I found this statement: assign XYZ = PQR_AR[44*8 +: 64]; What is the "+:" operator known as? I tried to find this on google, but I didn't get any relevant answer.
shailendra
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm using as Video RAM for a VGA module): module text_ram #( parameter A = 10, …
Hugo Sereno Ferreira
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What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To provide some context, I'm interested in the…
VHDL Addict
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What's the motivation in using Verilog or VHDL over C?

I come from a programming background and have not messed around too much with hardware or firmware (at most a bit of electronics and Arduino). What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over a…
Reflection
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Verilog: XOR all signals of vector together

Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out: assign XOR_value = large_bus[0] ^ large_bus[1] ^ ... ^ large_bus[63] ? I'm especially interested in doing this for…
Randomblue
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Concatenate signal n times in Verilog

Given a signal wire [7:0] dummy, how can I concatenate it n times? That is, is there a notation for the following: {dummy, ..., dummy} // n times ?
Randomblue
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SystemC vs other HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and run it in an FPGA. Everything is going well so far,…
Andrés AG
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