Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [verification]

Assurance of satisfiability of all the expected requirements in either software or hardware systems.

It encompasses all the disciplines whose goal is to assure either hardware or software fully satisfy all the expected requirements.

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Electronics System Standards Compliance: Certification, Testing & Verification

Please note: this question has to do with the technical compliance aspects of the consumer electronics indsutry, and as such, I believe is within scope for this site. This question is about compliance, and Compliance is absolutely a qualitative…
smeeb
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What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To provide some context, I'm interested in the…
VHDL Addict
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Why is BMC/k-induction used in RTL formal verification?

One popular approach for proving safety properties in formal verification of RTL designs is a combination of BMC and \$k\$-induction, which appears to stem from "Checking safety properties using induction and a SAT-solver". This boils down to trying…
ferris
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How does a non-designer understand a chipset's functionality?

I once met a person who told me as a part of his work he was testing and characterizing analog chips which include all sorts of components like ADCs, DACs, regulators ect. embedded in one chip. But he said he doesn't know how to design such a chip…
floppy380
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Is there a "standard" way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using VHDL or Verilog/SystemVerilog? Or is it better to…
quantum231
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Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing thorough automated tests for my code. I have been…
J. Doe
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EMC testing vs. EMI testing

What is the difference between EMC testing (Electromagnetic compatibility) and EMI testing (Electromagnetic interference)
Sean McDonnell
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Testing paradigms for consumer electronics

I am brand new to EE/ECE (my background is software) and I am curious about how real-world electronics testing takes place. In software, there are many different types of tests that a piece of code should be run through to make sure it's of high…
smeeb
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How exactly does SystemC/SystemVerilog make the verification flow less laborious task

Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design techniques into the digital IC design domain. What…
quantum231
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What is formal verification of hardware?

I read that testing and verification are different but in what way? I read that somebody writes theory to prove that the hardware is "correct" but how is that done? I tried reading Wikipedia and googling about it but I either end up in too advanced…
Niklas Rosencrantz
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Circuit Testing, Verification & Certification Standards for Biomedical Devices

Please note: I would have posted this question on HealthIT.SE but they are apparently now closed for business, and I believe this site is the next most appropriate place to ask this. I believe this question is on topic because it involves circuit…
smeeb
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How to convert Sequential circuit into a combinational circuit?

My question in general asks how to transform a sequential circuit/FSM into a combinational circuit. The reason why I'm asking is in SAT solving, we can use only combinational circuits. And so in order to use sequential circuit, we need to "unroll"…
Xpleria
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Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this before lunch). It's the only module in the…
Krunal Desai
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How to test a CPU watchdog on board?

The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span. I want to be sure, that it is enabled and working properly. What is a good method to verify…
Jonas Stein
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How can a IC (or transistors or diodes) design make it difficult for a malicious manufacturer to subvert it undetected?

Introduction This is a spin of from my question on security.se. To give more context: If I have a threat model where the adversary wants to corrupt computation or steal information does not want to be noticed at all (or at least until I made…
Gabriel Schulz
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