Highest Voted 'uvm' Questions - Electrical Engineering Stack Exchange

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What is the new constructor's argument rule in UVM?

I'm wondering why some new constructor has been implemented with argument and some new constructor has been implemented with no argument in UVM as the below example. class mem_monitor extends uvm_monitor; uvm_analysis_port #(mem_seq_item)…

system-verilog uvm

asked Mar 19 '22 at 01:52

Carter

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2

votes

1 answer

How to connect multiple interfaces within DUT in UVM?

I have two interfaces: virtual intf vif; virtual i2c_intf i2c_vif; I need to connect them at my top level. Currently, I am connecting it like below: module tbench_top; //creating instance of interface intf i_intf(); i2c_intf …

system-verilog uvm

asked Feb 16 '22 at 13:58

Carter

581
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1

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2 answers

How to use "question mark" in start method of UVM?

I am trying to modify the existing code using the start() method in UVM. Basic code is below: function void build_phase(uvm_phase phase); uvm_config_wrapper::set(this, "tb.chan?.rx_agent.sequencer.run_phase", "default_sequence", …

system-verilog testbench verification uvm

asked Aug 02 '23 at 04:03

Carter

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3 answers

Problem overridding parametrized UVM objects

In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence 'MySeq' and a derived sequence 'MyConsecSubFrmSeq'. …

simulation system-verilog testbench verification uvm

asked Jul 04 '23 at 04:34

أحمد المحمودي

73
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1

vote

1 answer

How to sample the read data from blocking logic safely by using the interface of SystemVerilog?

I'm trying to read data from combinational logic. module my_reg(; ... output reg [31:0] rdata; ) .... always @(data) rdata = 32'h18; and this dut's value is interfaced with a testbench. module test; ... my_interfcae _if(); my_dut…

verilog system-verilog soc testbench uvm

asked Feb 21 '23 at 10:24

Carter

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1 answer

Issue of reset value assignment in the UVM register model

I came across a register model example as below. Register ureg1_t looks like: class ureg1_t extends uvm_reg; rand uvm_reg_field destination; rand uvm_reg_field frame_kind; rand uvm_reg_field rsvd; virtual function void build(); …

system-verilog uvm

asked Jul 02 '22 at 02:25

Carter

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1 answer

How do I implement an access of register if it has the multiple access options in UVM IP-XACT?

I'm trying to understand the IP-XACT User Guide schema for making the RAL model. Especially, if I have a register called DEV_STAT as below, I understood that DEV_STAT contains the DEV_ID and REV_ID bit fields. Q1) What if DEV_ID is RO (Read_Only)…

uvm

asked Jun 08 '22 at 05:06

Carter

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1 answer

How to print uvm_tlm_analysis_fifo properties with `uvm_info() in UVM?

I'm stuck on the print properties of uvm_tlm_analysis_fifo handle with `uvm_info(). I made a simple sequence item as below. class simple_sequence_item extends uvm_sequence_item; rand bit[9:0] address; rand…

verilog system-verilog uvm

asked Jun 02 '22 at 08:42

Carter

581
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1 answer

How to finish the forever statement on run_phase in UVM?

I'm trying to understand forever statement in raise_objection()/drop_objection(). I thought that the forever statement will be finished after drop_objection(). But, the below forever statement does not finish. forever begin …

system-verilog uvm

asked May 27 '22 at 05:13

Carter

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1 answer

Auto Prediction Register model update Issue in RAL

I'm trying to understand the auto prediction concept in UVM RAL model, and I came across the Auto Prediction Register model update Issue in https://youtu.be/hrxhUE_RHyY?t=145. But, I didn't understand "UVC sequences which access registers will not…

system-verilog uvm

asked May 23 '22 at 07:31

Carter

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vote

1 answer

How to setup a Backdoor Access within UVM RAL model?

I'm trying to understand Backdoor Access within UVM RAL mode example https://www.edaplayground.com/x/jy3U . In uvm_guide, it wrote that if HDL paths are used, the root HDL paths must be specified in the environment that instantiates the register…

system-verilog uvm

asked May 19 '22 at 11:38

Carter

581
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1

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1 answer

How to print a created handle information in UVM?

I create an object handle in UVM usually with new or create to allocate memory. Is there any possible way to print about created handle information? For example, I made the below example. task body; i2c_packet pkt; pkt =…

system-verilog uvm

asked Feb 26 '22 at 10:08

Carter

581
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1

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1 answer

How to partial port connect by using interface bundle?

I'm trying to connect DUT's port list with interface by using bundling. The current problem is that the DUT was implemented with lots of ports. It's almost 1500 more. I want to connect a partial bundle interface such as i2c interface, ahb interface,…

system-verilog uvm

asked Feb 18 '22 at 10:54

Carter

581
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1 answer

How to start task in virtual sequence from testcase?

I'd like to execute a virtual sequence's task as below: class MYTest extends uvm_test; my_base_ahb_vseq_c my_base_ahb_vseq; …

system-verilog uvm

asked Jan 23 '22 at 10:11

Carter

581
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0

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1 answer

How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer. The monitor message should only appear when a command(Read/ Write) is issued. because this monitor connected to Scoreboard, I need the monitor signals when they are issued in…

verilog soc amba uvm ahb

asked Feb 18 '23 at 16:03

Carter

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Questions tagged [uvm]