Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it. There are two basic approaches, static timing analysis and dynamic timing analysis.

Static timing analysis simply considers the topology of the circuit and the worst-case characteristics of each component, without regard to the actual states of the signals.

Dynamic timing analysis performs a simulation of the circuit that takes into account the specific component delays for the actual combinations of input signal states encountered during the simulation.

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Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a simple scaler to achieve an effective pixel…
Hugo Sereno Ferreira
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Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns. During the 6th positive edge, we see that the data (or X) is…
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Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.) I tried to analyze their behaviors at the clock edges. For D flip-flop 1, At the rising edge, because the clock needs…
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Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design clock) can be implemented on my Artix-7 200T. If I…
Paebbels
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Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are timing constraint violations near the DAC interface…
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Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs bits than there are physical pins, so Quartus II…
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Vivado constraints wizard suggests a lot of nonsense generated clocks

I'm trying to apply timing analysis to a RISC-V MCU I have designed in SystemVerilog, in Vivado, for a Basys 3 board. My design contains several generated clocks, which are made by dividing the system clock (100MHz) by a number. I use fabric to do…
Martel
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How to write to a Hitachi HM628128A SRAM?

I'm working with a Hitachi HM628128A SRAM chip. According with the datasheet, the function table is How do I write data in the chip? Must I execute "write cycle (1)" and then "write cycle (2)", or can I just choose one of the two methods?
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Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with flip flops. I thought of not using PLL to make my…
Meenie Leis
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my external circuit has? What I hopefully understood…
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock): always @(posedge…
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Synchronize Outputs of Separate FPGAs Within 1ns

Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution. I'm trying to synchronize the outputs of two physically…
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waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm also easily convinced that trace length-matching…
lamont cranston
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How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock speed (~50MHz). I have been looking at the post…
Zack Newsham
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What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which the output pin of one register feeds the clock…
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