Questions tagged [testbench]
106 questions
11
votes
3 answers
How do I protect myself when testing a PCB that involves an AC line?
I have to test prototype PCBs that convert household AC into several DC voltage levels.
I concern about my safety when working with AC and would like to know how to properly setup a testbench that, for example, will trip a circuit breaker or break a…
Natthapol Vanasrivilai
- 235
- 1
- 8
8
votes
3 answers
VHDL: What is correct way to model open collector output for FPGA?
I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.
How should open collector output be defined in a VHDL for an FPGA?
How should open collector output be pulled high in testbench? i.e how model…
quantum231
- 11,218
- 24
- 99
- 192
6
votes
3 answers
Writing synthesizable testbenches
I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing thorough automated tests for my code. I have been…
J. Doe
- 61
- 3
5
votes
2 answers
Temporary PCB connections for testing
I want to be able to perform tests on assembled PCBs with a custom tool. the test would take seconds, and would be done manually by connecting a cable between the tool and PCB.
My question is what sort of connectors or similar are used for this…
Jodes
- 5,044
- 9
- 48
- 75
3
votes
1 answer
Model running slower than RTL in SystemVerilog
I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The regression suite took around 20 hours to…
Ashhad Khan
- 129
- 10
3
votes
1 answer
VHDL Clock Divider Problem
I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clkdiv is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clkout : out STD_LOGIC);
end…
dubistweltmeister
- 81
- 8
3
votes
2 answers
How can I improve my testbench for testing a 1024x4 RAM memory in Verilog
This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog".
Basically, I have modified the previous solution in an attempt to test a 1024x4 RAM memory, which uses coincident…
aLoHa
- 587
- 1
- 6
- 16
3
votes
1 answer
Pass parameters to covergroups in SV Testbench
I am trying to create a parameterized covergroup in my testbench as follows:
covergroup CG (input int id);
cp1 : coverpoint tb.gen_block_mem[id].var_x[3:0];
endgroup : CG
CG CG_0 = new(0);
CG CG_1 = new(1);
This fails in elaboration as…
Shashank Gangrade
- 43
- 5
3
votes
1 answer
Simulating a thermopile on the bench -- is this a reasonable/reasonably accurate way to do it?
Primer
Most people know about 24V HVAC control systems, as that's what's commonly found on furnaces, heat pumps, central air conditioners, and other such systems. If you have electric unit or radiant heat, you may have seen line-voltage thermostats…
ThreePhaseEel
- 8,858
- 4
- 26
- 41
2
votes
1 answer
Need help debugging Verilog I2C slave code
As you can see in the waveforms and the code after the start (busy line goes high) condition occurs, I start sending the slave address bit by bit in the testbench through the SDA line, and this needs to get stored in the address register. And in…
Sushant Chachadi
- 45
- 5
2
votes
1 answer
Architecture for a virtual 3-phase motor
I would like to construct an electronic virtual 3-phase motor for testing VSD/servo drive systems in the workshop, where the actual motor is not available for testing (e.g. because it is on a running machine, or it hasn't arrived yet, etc).
Let's…
Cliff Pennalligen
- 131
- 4
2
votes
1 answer
Why I am having x as output from ReLU?
I am trying to test ReLU, but it always gives 'x' for the output.
//Relu.sv////
module ReLU # (parameter Width=8)
( input signed [2*Width -1:0] dataInput,
output reg signed [2*Width -1:0] dataOutput
);
always @*
begin
…
Ghadeer Ali Jaradat
- 35
- 4
2
votes
1 answer
My test bench in VHDL is always showing U for all values
I am learning VHDL for a University course.
My code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity operations is
Port (x : in STD_LOGIC_VECTOR ( 2 downto 0) ;s : in…
Nour Samir
- 23
- 3
2
votes
1 answer
Resources for learning Open Source VHDL Verification Methodology (OSVVM)
I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following:
Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based simulations? If so, how pls (any tutorials…
Arvind Gupta
- 97
- 1
- 5
2
votes
1 answer
Problem in implementing D Flip Flop with asynchronous Reset using Verilog
I was implementing the D flip flop with asynchronous reset in Verilog. This is the code that I put in:
module d_ff_A (input Clock, input D, input Rst, output Q);
wire Clock, D, Rst;
reg Q;
always @(negedge (Rst) or posedge (Clock))
begin
if…
Ashutosh Singh
- 23
- 4