Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

It is defined by IEEE 1800-2012 and with the exception of some keywords, is a backwards-compatible superset of , IEEE 1364-2005.

435 questions
16
votes
8 answers

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To provide some context, I'm interested in the…
VHDL Addict
  • 161
  • 1
  • 1
  • 5
14
votes
2 answers

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that == tests for only 1 and 0, while === tests for 1, 0, X, Z. So how is that similar to the shift operator?
daut
  • 151
  • 1
  • 1
  • 8
8
votes
3 answers

Are there any free simulators for SystemVerilog?

Are there any free simulators available for a hardware design coded in SystemVerilog? In particular, I need SystemVerilog's dynamic arrays.
KevinSim
  • 353
  • 4
  • 12
8
votes
3 answers

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. For example: x = #10 y; will be considered as x =…
Anand
  • 227
  • 1
  • 4
  • 5
6
votes
3 answers

Systemverilog to Verilog translation

I have a code block (multiple files) in Systemverilog. I am using the Xilinx tool flow that does not understand SystemVerilog (an old part). Is there a tool (or a rule book) I can use to convert the SystemVerilog to standard Verilog-2001 code ?
boffin
  • 477
  • 1
  • 7
  • 15
6
votes
2 answers

Is there a "standard" way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using VHDL or Verilog/SystemVerilog? Or is it better to…
quantum231
  • 11,218
  • 24
  • 99
  • 192
6
votes
6 answers

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am really lost when it comes to implementation. I…
ironstein
  • 309
  • 4
  • 14
6
votes
2 answers

systemverilog structure initialization with default = '1

Can someone shed light on what this SystemVerilog code should do: typedef struct { logic [15:0] a; logic [15:0] b; logic [15:0] c; } my_struct; localparam my_struct s = '{default:'1, c:0}; Is this legal? I can't quite figure out the spec well…
nachum
  • 187
  • 1
  • 1
  • 4
6
votes
2 answers

Difference between HVL and HDL

Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
sarthak
  • 3,646
  • 4
  • 19
  • 31
5
votes
1 answer

Why don't I see the clocking block input skew in waveforms?

That's the code: module flipflop (input logic clk, reset, input logic [7:0] qin, output logic [7:0] qout); timeunit 1ns; always @(posedge clk or posedge reset) if (reset) qout = '0; else qout =…
Chengineer
  • 107
  • 5
5
votes
1 answer

Nonblocking ++ equivalent in SystemVerilog

The ++ operator in Systemverilog is blocking. Is there a nonblocking equivalent to it, or are we bound to use the more verbose x<=x+1 form if we want to keep it nonblocking? Refer to IEEE Std 1800-2017, section 11.4.2 Increment and decrement…
shaiko
  • 459
  • 1
  • 6
  • 15
5
votes
2 answers

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

This question explains how to use Verilog parameters to combine constants from different modules at compile time. I am wondering if it is also possible to use conditional statements to modify parameter values at compile time. Specifically, if the…
Chris Fernandez
  • 1,316
  • 14
  • 32
5
votes
3 answers

Undefined signal in simulation

I am trying to verify a design written in VHDL using SystemVerilog's assertions. I have a problem when I have a non-defined signal'X.' Just for example here is the code of a comparator: entity FP_comparator_V2 is port ( comp_in1 …
mariam
  • 51
  • 1
  • 2
5
votes
2 answers

System Verilog generic modules and unused ports

I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like full, empty, almostFull and almostEmpty. However sometimes not all of the output signals are used,…
ted
  • 259
  • 2
  • 11
5
votes
2 answers

How exactly does SystemC/SystemVerilog make the verification flow less laborious task

Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design techniques into the digital IC design domain. What…
quantum231
  • 11,218
  • 24
  • 99
  • 192
1
2 3
…
28 29