Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [synthesis]

Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.

Transform a high-level design description (e.g. VHDL or Verilog) into a design implementation in terms of logic gates, typically by using a computer program called a synthesis tool. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs.

Reference: https://en.wikipedia.org/wiki/Logic_synthesis

250 questions
20
votes
3 answers

VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc. I use std_logic at top level ports, but internally I was using ranged integers all over the place. However, I've stumbled across a few references to…
darron
  • 3,491
  • 2
  • 29
  • 42
15
votes
2 answers

How can I specify "don't care" signals in VHDL?

In Logic Design courses we all learned that it is possible to minimize a logic function, for example by using a Karnaugh map or the Quine–McCluskey algorithm. We also learned that "Don't Care" values increase the minimization potential. For example…
Fritz
  • 768
  • 1
  • 5
  • 17
14
votes
3 answers

Why does digital equipment have more latency than analogue?

Is the explanation that the digital equipment takes longer to propagate? For instance, a software synthesis is very slow compared to a hardware synthesis.
Niklas Rosencrantz
  • 1,694
  • 6
  • 33
  • 62
12
votes
3 answers

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not required.). If not for the full language, how about…
hotpaw2
  • 4,731
  • 4
  • 29
  • 44
11
votes
2 answers

Why do non-synthesizable commands even exist in VHDL?

VHDL includes commands like access ,new and shared variable that are never synthesizable or while and loop that are still somewhat synthesizable but are never recommended to to be used. So why do they even exist if they cant be synthesized and are…
Sepand.S
  • 161
  • 8
10
votes
2 answers

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable is assigned to a signal or another…
nurabha
  • 887
  • 4
  • 14
  • 29
10
votes
1 answer

Why is synthesis so slow compared to compilation?

Even simple HDL designs takes hours to synthesize, while compiling the Linux kernel on the same machine completes in under 15 minutes. Please explain why with a breakdown of the tasks the synthesizer has to carry out.
Björn Lindqvist
  • 247
  • 1
  • 8
9
votes
5 answers

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (Behavioural simulation) but does not synthesize…
ironstein
  • 309
  • 4
  • 14
8
votes
1 answer

Is the initial block in Verilog sythesizable?

I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-synthesizable Verilog constructs (from the book Digital Logic Design Using Verilog by…
Sandeep I
  • 101
  • 1
  • 7
8
votes
2 answers

What is the difference between reg and wire after synthesizing?

Assuming i have these two codes: module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule and the second one is: module reg_combo_example( a, b, y); input a, b; output y; reg y; wire a, b; always…
0x90
  • 725
  • 3
  • 11
  • 25
7
votes
1 answer

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level netlist, or is there a specific HLS synthesis tool?…
oawad
  • 71
  • 1
6
votes
1 answer

Empty Netlist Vivado Design Suite

I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem is that once I perform the synthesis, the…
camillo_benso
  • 77
  • 5
6
votes
3 answers

Open Source verilog synthesizer

I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no longer supports synthesis. I have found the gEDA…
slashoofpez
  • 131
  • 1
  • 4
6
votes
2 answers

FPGA register initialization

I have to ask and understand it once and for all because I encountered a few opinions about this subject: When I'm designing FPGA with Verilog or VHDL there is any meaning to: Verilog -> initial block VHDL -> `:=` in the signal declaration…
Michael Rahav
  • 505
  • 3
  • 14
6
votes
2 answers

VHDL optimization

If I need to perform the same function on a number of different signals in a VHDL design will placing them in a vector affect synthesis optimization in any way? As as example, let's say I'm trying to simulate a real-world circuit that's built up…
Mark Feldman
  • 215
  • 2
  • 6
1
2 3
…
16 17