Questions tagged [synplify]

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at toplevel in the…

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: module arrtest(clk, led); input clk; output reg led = 0; reg [3:0] arr_index = 0; reg [7:0] intervals [0:9] = {8'd125, 8'd128, 8'd200,…

I'm trying to infer the usage of a RAM block of my FPGA, but I fail to understand what are the hints needed. I use Synplify Pro as my synthesis tool. If I'm not mistaken, this is a dual port synchronous RAM that I need to infer. library ieee; …

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which parameter value is wrong. For the Quartus I have write…