Questions tagged [synopsys]
6 questions
2
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0 answers
Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits
I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my designs — I have been able to successfully…
Natasha A.
- 21
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1 answer
HSPICE command naming weirdness
I have a simple digital invert circuit using ASAP7 nmos and pmos transistors. When I use Synopsys HSPICE to simulate the below script, it throws an error Definition of model/subckt "nmos_rvt" is not found for the element "xinv1^xm1". Please specify…
user2698
- 113
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1
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1 answer
How to compile .ccf file using CMI in Sentaurus TCAD?
I have gone through the Compact Model interface manual provided by Synopsys. They only mentioned to compile the .ccf file using cmi compiler and generate .so.arch file. However, there are no more details regarding this. I couldn't find much help…
Siddhanta roy
- 13
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1 answer
how can i make compile stage shorter in VCS (synopsys) after logic changed?
if I changed few lines from a specific Verilog of design and now I want to recompile, can I compile just the related files or I need to compile the whole design again?
i'm using VCS tool by Synopsys.
asif evgy
- 11
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Can't set clock network delay to zero during synthesis
I am using Synopsys Design Compiler for synthesizing my design. I have read in the User's guide of DC that by default it assumes ideal clocking during synthesis meaning that clocks have zero network latency. However, when doing post-synthesis…
O'ara
- 1
0
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1 answer
Clock network remains at x when applying fast clock frequencies
I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of faulty behavior could be observed by increasing the…
O'ara
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