A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.
Questions tagged [state-machines]
250 questions
33
votes
8 answers
Why is the output of stateful elements often named Q?
In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have their "state" called Q. I suspect there is a…
Gyom
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25
votes
11 answers
VHDL interview question - detecting if a number can be divided by 5 without remainder
I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they don't want you to use mod or rem) and while I did…
nettek
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10
votes
2 answers
How to choose between Mealy and Moore state machine
I know the basic differences between Mealy and Moore FSM (Finite state machine). What I want to understand is the following:
Pros and cons of using Mealy over Moore and vice versa
In which situation Moore is more suitable than Mealy and vice…
nurabha
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9
votes
5 answers
Interrupt handling in microcontrollers and FSM example
Initial question
I have a general question about the handling of interrupts in microcontrollers. I am using the MSP430, but I think the question may be extended to other uCs.
I would like to know whether is or not a good practice to enable/disable…
Umberto D.
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9
votes
3 answers
Pressing same key rows at the same time
I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition pin4pin6pin7pin2 = "0000" I switch to next state…
Anarkie
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8
votes
1 answer
How do I design a clocked synchronous state machine for a combinational lock?
I need help in completing a task, I’m stuck on quite a few things. Since I’m very new to this topic on finite machines.
I’ve attempted the state diagram, state table, transition table, K-map values and the k-maps (Karnaugh - map) themselves.…
Omuse
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8
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2 answers
Embedded programming state machines
I am looking at implementing a non-trivial finite state machine (specified as a UML hierarchical statechart) on a 32-bit MCU with gcc.
Are there any rules of thumb what works better and what works less well? My gut says that a switch-based (or even…
ARF
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6
votes
1 answer
conversion from Moore To Mealy
Can somebody please explain how can I convert from Moore FSM to Mealy FSM and vice versa?
hello
6
votes
3 answers
How can I convert a 4-digit BCD number to Binary in hardware? (using 74LS ICs and GAL22V10 ICs)
As the title suggests, I need to convert a 4-digit BCD number to binary.
I am aware of the doubble-dabble algorithm (https://en.wikipedia.org/wiki/Double_dabble), and that if you use it backwards you can convert from BCD to binary.
The algorithm…
LittleBigTech
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6
votes
3 answers
Moore vs mealy, why the output is delayed in the former?
I am not an engineer (software developer myself) but would like to understand why moore machine output is delayed.
I know that in Moore's machine, output depends only on the state, while in Mealy's machine, it depends on both the current input and…
John V
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6
votes
2 answers
Is there a "standard" way to verify HDL of a state machine?
State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using VHDL or Verilog/SystemVerilog? Or is it better to…
quantum231
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5
votes
2 answers
'1011' Overlapping (Moore) Sequence Detector in Verilog
I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog .
The FSM that I am trying to implement is as shown below :-
Verilog Module :-
`timescale 1ns / 1ps
module seq_detector(
input x,clk,reset,
output reg…
Abhishek Chunduri
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5
votes
2 answers
'1011' Overlapping (Mealy) Sequence Detector in Verilog
I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog.
The FSM that I'm trying to implement is as shown below :-
Verilog Module :-
`timescale 1ns / 1ps
module seq_detector(
input x,clk,reset,
output reg z
);
parameter…
Abhishek Chunduri
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5
votes
3 answers
State Machine with D Flip Flops; how to deal with race conditions
Consider a state machine whose entire state is kept in a collection of edge-triggered D flip-flops. The outputs of these are fed into a combinatorial network which fully determines the next state, and is fed back into the flip-flops' inputs. On…
Manuel Menzella
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5
votes
2 answers
How to send a packet every n clock cycles in verilog?
I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module and I have to decode the required read response…
frisco_1989
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