Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.
Questions tagged [sram]
200 questions
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What's the catch with FRAM?
After recently acquiring an MSP430 Launchpad I've been playing with various microcontroller projects. Unfortunately, the MSP430G2553 only has 512 bytes of RAM, so doing anything complex requires external storage.
After looking at SPI and I2C SRAM…
David Given
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Why are SRAM based FPGA used more than NVM based FPGA?
SRAM based FPGAs need to load the bitstream again after power off. Meanwhile the Non-Volatile based one don't need that.
I wonder, why are more experiments and security research done on the SRAM FPGA than the the NVM based one, it seems that the…
Lavender
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SRAM isn't blank on powerup, is this normal?
I had finally finished my Z80 memory board, but I was disappointed to see that it wasn't working properly (simple NOP test with the address lines connected to some LEDs) as the counter quickly spiraled out of control instead of incrementing as it…
KeatonB
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Using CCM (Core Coupled Memory) in STM32F4xx
STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.
What is the reason to add additional SRAM as CCM?
Does it increase performance and if that it's the case…
user13630
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Does pin order matter at all for this RAM?
I am trying to route a pic32 chip to a 128kB SRAM chip and having a bit of a hard time getting all 17 address lines and all 8 data lines connected. I am trying to tie the first 16 address pins to portB pins 0-15 and the data pins to portD 0-7.…
captncraig
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Which SPI mode to use?
I'm interfacing a 23LC1024 SPI Serial SRAM with a PIC18, using the C18 compiler and the built-in functions from as described in the Compiler Libraries, section 2.8:
OpenSPI1 - Initialize the SSPx module.
void OpenSPI1(
unsigned char…
user17592
8
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4 answers
Why does this SRAM chip have more physical bits than declared by the manufacturer?
I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.)
The manufacturer clearly identifies this chip as 256Kbit.
Reading through the datasheet it clearly says "32768 x 8" which confirms my scan result - but…
Shlomi Hassid
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Why are the SRAM data and address pins numbered?
As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g.…
fadedbee
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Running executable from external SRAM
I have an STM32 dev board with some external SRAM. I would like to execute my code from that external SRAM, but my processor only supports booting from the Flash, internal SRAM or System memory (a part of the internal SRAM).
What is the easiest way…
Randomblue
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SRAM and Flip-Flops
Still learning, but this question is bugging me.
I finally sort of understand how Flip-Flops work, and how that is used to maintain Shift Registers and such.
From the wiki page:
"Each bit in an SRAM is stored on four transistors"
Why four? SRAM is…
user3073
7
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2 answers
Why are the challenges in using SRAM over DRAM for main memory?
Historically, when compared to DRAM (dynamic ram), SRAM (static ram) is more expensive with a lower density, but it's much faster and more efficient. As a result, SRAM is reserved for devices, such as processor caches and microcontrollers, where…
user148298
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Why not SRAM for FPGA in image processing?
I'm beginning with VHDL coding and I've done some basic image processing on my development board.
I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM.
For example, I'm using a FPGA dev board from TERASIC and it uses…
user17828
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Data bus between uC and SRAM: what happens when both are writing concurrently?
My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the bus. When reading, OutputEnable# is low and the…
tschaboo
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Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are anywhere from 10 times to 100 times faster than RAM…
Robin Rodricks
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Using SDRAM with a MC68000
I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. SRAM of that size is hideously expensive (around…
Tristan
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