Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [spartan-6]

Spartan-6 FPGA Family by Xilinx

"Spartan®-6 delivers an optimal balance of low risk, low cost, and low power for cost-sensitive applications, now with 42% less power consumption and 12% increased performance over previous generation devices. Part of ’s All Programmable low-end portfolio, Spartan-6 FPGAs offer advanced power management technology, up to 150K logic cells, integrated PCI Express® blocks, advanced memory support, 250MHz DSP slices, and 3.2Gbps low-power transceivers."

See also the product official website.

48 questions
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What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. As you can see the above diagram, there are 10:5…
Carter
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Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a critical warning or can I proceed with dumping the bitfile…
Sai Gautam
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Spartan-6 -- Map failed due to using a non-clock pin for a global buffer instance

I'm trying to use Spartan 6 (TQG144) PLL to generate a high speed clock. I used IP core generator to config the PLL. Here is the simple VHDL code I have to use the generated component: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity clk_test is …
Sina
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Poor clock output from Spartan6 FPGA

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it was not as I expected. FPGA Clock (system): 100…
dDebug
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Help with multiple receiver channels and single storage architecture

I want to build a datalogger that has multiple receiver channels that run on serial communication protocol RS232 and then collect the information from the channels in a single storage that would be accessed by another controller whenever it gets…
MavenMerkel
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Problem with connecting clock divider generated by CORE Generator to I2S design for Spartan 6

I'm trying to connect clock divider generated by CORE Generator to I2S receiver and I2S transmitter on Spartan 6. The PLL_BASE is connected via ODDR2 module, as adviced. Both receiver and transmitter work when clocks are divided without block from…
Peter
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Can not keep pin LOW during FPGA configuration

I would like to have a control signal that stays low all the time and goes hi only when I tell it to. Initializing the pin in the entity does not seem to set the value to zero (xc6slx25-3ftg256): Entity myEntity IS PORT( -- clock and other IOs …
Nazar
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Power supply for FPGA

I have a Spartan 6 FPGA (XC6SLX9-2TQG144) and I'm designing a power supply for it. Let's assume that I will utilize all of its logic (very possible) and I want to clock it as fast as possible (around 350MHz). How can I estimate the power (number of…
zupazt3
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VHDL Block RAM Inference

I am storing a 16k constant sine table of 14 bit signed vectors in a package. I use this package in my module to read out the array in a clocked process But I get this warning during synthesis and my synthesis is taking a long time - The RAM will…
Sai Gautam
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Xilinx XST won't infer block ram

I'm having trouble getting the design of my FPGA 80's computer to fit on a Papilio Duo board which is a Spartan 6 - xcs6slx9. The problem stems from RAM being inferred as distributed instead of block. Short version : I'm using a generic entity to…
Brad Robinson
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18bit Serdes - Xilinx Spartan6

In a project with FPGA stereo vision I use two MT9V032 cameras. The cameras are connected as in the application example in the data sheet. In stereo output mode the data length is 18bits long. There is one start bit and one stop bit. So there are 8…
Timm
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Xilinx clocking wizard - How to connect clkfb_in and clkfb_out

I created a VHDL design which needs a 50 MHz clock input. The Spartan-6 I'm working on gives me a 100 MHz clock signal, so I used the Xilinx Clocking Wizard to get a 50 MHz clock. When I choose "No Buffer" two additional ports will be created - a…
nablahero
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Slow clk output (Spartan-6)

I have a design which looks like this: -controller --Module1 ---SubModule1.1 ---SubModule1.2 ----SubModule1.2.1 --Module2 ---SubModule2.1 ---SubModule2.2 ---SubModule2.3 ---SubModule2.4 --Module3 ---SubModule3.1 ---SubModule3.2 ---SubModule3.3 So I…
nablahero
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IP Core Generator fails with Error

I'm working on a project using a Spartan-6. I created a FIFO with the IP Core Generator (New Source -> IP Core -> FIFO -> Generate). The LOG looks like this The IP Catalog has been reloaded. Qt: Untested Windows version 6.2 detected! INFO:sim:172 -…
nablahero
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Spartan 6 DCM unstable clock output

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input clock. It works fine as long as the input clock is…
Sai Gautam
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