Questions tagged [spartan-3]
15 questions
2
votes
2 answers
Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?
I am trying to find SPI connections to download my program to Xilinx XC3S50A-4VQG100C but can’t figure which pins are SPI pins.
Newbie alert : I just started learning FPGA and am trying to build my own dev board from the scratch ( I always learn…
Aug
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2
votes
1 answer
Trouble running picoblaze code
I am running a simple picoblaze code where I am using two addresses and sending a high strobe on both the addresses, the assembly code has no loop, so technically my code should run ONLY once but the high signal on the addresses that I am using is…
alexhilton
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2
votes
1 answer
Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?
I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as RAMB16_S18_S18. I am using one port for both reading and writing (using write-enable)…
nanofarad
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1
vote
1 answer
Unknown problem with I2C on Spartan 3-E {VERILOG}
I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" received on LEDs i.e (I had an internal counter…
Ahmed Ali Abbasi
- 47
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1
vote
1 answer
How do I reset my registers on Digital Clock Manager output?
I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT.
The reset logic I'm using is shown here.
DigitalClockManager instance_name (
.CLKIN_IN(CLK_50MHZ),
.RST_IN(rst_in),
.CLKFX_OUT(clk), …
Ahmed Ali Abbasi
- 47
- 9
1
vote
0 answers
Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?
I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as an input and GCLK in the datasheet.…
nanofarad
- 18,062
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1
vote
1 answer
VHDL SPI xilinx spartan 3E
I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher.
I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. As far as I can understand from the RTL schematic…
Runsiv
- 11
- 2
0
votes
2 answers
3v3 JTAG interface on Spartan 3 FPGA
I have had issues with detecting a JTAG chain with 2 XC9500XL CPLDs and 1 Spartan 3 FPGA on a custom pcb.
I made a mistake thinking the Spartan 3's JTAG was 3v3 instead of 2v5 and connected the FPGA directly to the 3v3 JTAG.
Xilinx wrote an…
Clément Chaine
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0
votes
0 answers
Why are 30 MHz crystal oscillators commonly used with FPGAs?
I am new to FPGAs. I am working on a clone board that has a Spartan 3AN.
There is a 30 MHz crystal oscillator on board.
I have checked another boards and noticed that 30 MHz is commmonly used.
Is there specific reason to use a 30 MHz clock…
0
votes
1 answer
VHDL: signal doesnt keep a value
hi first of all english is not my languaje.
im using a SPARTAN 3E as develop board
i tried to make a FSM that changes
the state with a counter called "T" (somethig like a pseudo-processor) and use a button as pulse to increment, in one case the…
menymp
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0
votes
1 answer
Clock Implementation Design Warning on Spartan 3E
I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager.
These are my UCF designations :
NET "CLK_50MHZ" LOC = "C8" | IOSTANDARD =…
Ahmed Ali Abbasi
- 47
- 9
0
votes
1 answer
Video Display Buffer-VGA Port Interfacing
I am trying to get a basic understanding of how VGA port interfacing works.I have started reading SPARTAN 3 VGA Port Interface. I get the function of horizontal and vertical syncs, and the subsequent clock requirements, but I still don't understand…
FechP
- 11
0
votes
2 answers
BASYS2 - Verilog: how to properly edit ucf file?
I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some
trouble with FPGA. Actually, not with FPGA but with Compiler and ISE. As
you can see in the…
Alper91
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-1
votes
2 answers
NOT Gate implementation BASYS Spartan 3E
this is my first post here. I am new to FPGAs. I would like to implement a NOT gate on the BASYS (Spartan3E-100) FPGA. I've been looking at the tutorial HERE to work my way towards a synthesis. I wish to keep everything on-board, i.e. only use the…
Antillar Maximus
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-2
votes
1 answer
How to change status of pin in Spartan 3E FPGA
Verilog Code:
`timescale 1ns / 1ps
module blink (customClk, LED, statusPIN);
input customClk;
output statusPIN;
output LED;
reg [31:0] counter;
reg LED_status;
initial begin
counter <= 32'b0;
LED_status <= 1'b0;
end
always @ (posedge customClk)…
Dipnarayan Das
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