The Spartan series's are low-cost FPGAs from Xilinx. Specify which series and part you are using.
Questions tagged [spartan]
91 questions
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How to identify areas of a FPGA design that use the most resources and area?
I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package.
The design is also almost complete, however at the moment it will no longer fit in the…

Marcus10110
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FPGA, first steps
Well this is a continuation of my question on FPGA over here.
I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount of work with micro-controllers.
I spent the last…

Kevin Boyd
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9
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2 answers
Programming multiple FPGAs using JTAG
I have a JTAG chain connecting 4 Spartan 6 FPGAs that I program using ISE iMPACT. The software can program any strict subset of the 4 FPGAs in a row successfully, and in any order. However, when I attempt to program all four FPGAs, the DONE pin of…

Randomblue
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9
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2 answers
Transmitting HDMI/DVI over an FPGA with no support for TMDS
I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS differential signalling.
I read a lot online about…

tangrs
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8
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FPGA Logic Gate Count
I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that equate to? Or rther, how would I figure out the…

haneefmubarak
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How fast does a 64-bit multiply or divide execute on an FPGA?
When using a regular FPGA such as Xilinx Spartan 3 or Virtex 5, how many cycles does a double-precision floating-point 64-bit multiplication or division take to execute?
As far as I understand, the FPGA does not have a hard FPU and you need to…

Robin Rodricks
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8
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2 answers
Compare implementing a simple automation design on a MCU vs an FPGA/CPLD
I have been working with MCU's since the 90's, and I've recently ventured into the FPGA scene with the Spartan6 series chips from Xilinx. Assuming a simple factory automation design with sensors and motors, and some intelligence to link everything…

Kevin Boyd
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7
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3 answers
What is the meaning of speed grade marking on Xilinx FPGAs?
According to Xilinx FPGA product datasheets, the numbers on the 5th line as 4C or 5I stand for speed grade and temperature.I have a XC3S400 with 4C speed grade (4= standard speed, 5= High performance).
I want to know what exactly the standard speed…

Aug
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Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results
Overview
I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed in simulation only.
I have the following entry in…

drxzcl
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Preventing Verilog module from being optimised away
I have tried to put lots of inverters to stress test my Spartan 6 power supply as recommended here. Here is the basic module:
module inverter(
input wire clk
);
reg [7:0] inverted;
always @(posedge clk) begin
inverted <= ~inverted;
…

Randomblue
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6
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4 answers
Can I use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E?
I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator.
Is it possible to use something different? Note, all I need to do is get a .bit file.…

Earlz
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4
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Fix Conflicting IO Standards
I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD.
You can find all of the IOSTANDARD's available for Spartan-3E in this document.
Whenever I try to compile my project it…

MLM
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4
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Minimizing Logic in a Spartan-6 for a Game of Life Cell
While trying to learn FPGA programming, I've decided to implement a massively parallel game of life. Here's my first attempt:
entity LifeCell is
Port ( neighbours : in std_logic_vector(7 downto 0);
state : inout…

Hugo Sereno Ferreira
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4
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inout port in VHDL RS232 Module from Digilent
I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, but the VHDL code contains an 'inout' port.
I've…

trayres
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4
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3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?
I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far:
I'm looking at using a Spartan 6 GTP Tranceiver with copper (Cat6/6a). I've spent most of the past few days…

stanri
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