Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [skew]

19 questions
5
votes
2 answers

Routing USB, DVI and Ethernet signals on a large PCB vs using long cables

Properly routing USB, DVI and Ethernet signals over long distances (30 to 40 cm) on a PCB seems to be relatively challenging (skew, characteristic impedance, cross-talk, etc.). Yet using the standard off-the-shelf cables appears to allow proper…
user110091
  • 167
  • 1
  • 11
4
votes
1 answer

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final resolution of about 15ps! I will be measuring the…
Rocketmagnet
  • 26,933
  • 17
  • 92
  • 177
3
votes
2 answers

Is there a maximum differential skew in Ethernet communication?

I am working on a device that runs 100 Base-T. When routing the differential pairs I was wondering if there is a maximum differential skew specified somewhere and if so, what is it? Is there a formula, does it depend on transfer speeds etc.? I…
VicTic
  • 59
  • 5
2
votes
1 answer

PCIe Gen4: inter-pair skew: any limits?

For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either: 2 TX differential pairs (of different lanes) 2 RX differential pairs (of different…
Sandro
  • 5,519
  • 6
  • 24
2
votes
1 answer

Skew in half-bridge dead time generator in LMG5200EVM

The eval board for the GaN half bridge module LMG5200 (datasheet) contains the following circuit to generate dead time from a single PWM input. The half-bridge module itself has good propagation delay matching (2 ns) and fast switching (few ns).…
tobalt
  • 18,646
  • 16
  • 73
2
votes
0 answers

How is Alignment Marker Used for Deskew in Ethernet Protocol?

I've been reading through the 802.3 standards recently and am learning about alignment markers inserted as blocks in ethernet frames to deskew PCS channels. While I can find information about the bit-by-bit content of these alignment markets, how…
Dragonsheep
  • 301
  • 1
  • 7
2
votes
1 answer

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with triple redundancy). As I am not interested in…
Happy Techy
  • 29
  • 4
2
votes
2 answers

Combinational logic delay is greater than clock period

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors). My answer to…
titan
  • 137
  • 3
  • 15
1
vote
1 answer

How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there some standard (e.g. JEDEC-defined) limit to the…
Polynomial
  • 10,562
  • 5
  • 47
  • 88
1
vote
1 answer

PCIE Gen 2 Intra-Pair Skew

I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair: Considering the capacitors the skew is ~50 mills: this is the relevant part of the stack up for my question: the traces are on…
Firas Abd El Gani
  • 1,021
  • 7
  • 15
1
vote
0 answers

Lattice FPGAs -- How to control skew on signals routed to IO pins?

Working with: Lattice XP2-30 or XP2-40 Tentatively a BGA484; almost certainly some BGA 1mm-pitch package Synplify PRO, with SystemVerilog Skill level: Beginner / early-intermediate. If I have a custom design (that is, to be implemented in a…
Cal-linux
  • 2,029
  • 2
  • 20
  • 37
1
vote
3 answers

Calculating phase angle from instantaneous voltage

For background info I am an EE/CE that is 10 years out of school and has since worked writing firmware and dealt mostly with digital communications and signals, so now I am having to reach back to my (very) atrophied analog knowledge. I am working…
Whistler
  • 121
  • 4
1
vote
1 answer

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other placement constraints. The interface spec is 300ps…
Alex I
  • 3,341
  • 2
  • 36
  • 59
1
vote
1 answer

Skew angle in 3-phase AC induction outer rotor motor

I am working on a motor like the above stated. I have 3-phase winding on a 24 slot stator. I am now designing the rotor part. What skew angle should i use for a very smooth rotational torque? Is there a specific number of slots to be made on the…
J.K.
  • 21
  • 3
0
votes
0 answers

Useful skew is a concept for what phase of physical back-end design?

The calculation of useful skew takes into account the shortest and longest logic paths. Does this mean that if I need to use useful skew during the CTS phase, then I need to routing the logic cells? Is the same with skew scheduling?
Dawn Li
  • 1
1
2