Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [sgmii]

Serial Gigabit Media Independent Interface (SGMII)

Serial Gigabit Media Independent Interface (SGMII)

SGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise.

Current version 1.8 [Document Number: ENG-46158] from 27.04.2005:
Serial-GMII Specification 1.8 (27.04.2005) - no public link found
Serial-GMII Specification 1.7 (20.06.2001)

Read more:
- Wikipedia article

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The SERDES/transceiver design inside the Ethernet MAC controller

I'm a little confused about the "SERDES" interface between MAC and PHY chip, and I drew some figures to illustrate the connections which confuse me as shown below. The MAC controllers in 3 figures are the same, but the transceivers inside the MAC…
Nobody
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Broadcom Ethernet PHY link-up issue

We are using BCM5482SA2KFBG PHY for ethernet link in SGMII mode by selecting INTSEL = 2'b10. The PHY was supposed to establish a link upon power up using Autonegotitation without any management configuration. PHY auto-negotiates to 10Mbps half…
Sudarshan shenoy
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Can SGMII MAC communicate with 100BASE PHY at 1 Gb/s?

In the DP83TC811S-Q1 SGMII's datasheet it says Because the DP83TC811S-Q1 operates at 100 Mbps, the 1.25 Gbps rate of the SGMII is excessive. The SGMII specification allows for 100 Mbps operation by replicating each byte within a frame 10 times. So…
qand
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What values should be checked for SGMII signal compatibility?

How can I verify the DC electrical compatibility of the SGMII signal between PHY and MAC (within FPGA)? Here is the reference-design that I am working on. Page 40 is using a Marvel PHY that is obsolete. I would like to replace that PHY with TI…
student7
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Connection Ethernet MACs without using a PHY device

I am designing a board that utilizes an NXP LS1046a processor and multiple Kintex Ultrascale FPGAs. The plan is to connect the processors up to the three FPGAs via the 1Gbe links. Since they are all on the same board, the plan was to try and connect…
Matty
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SGMII Termination - Not understanding recommendation

I am going to be using a processor that has a few SGMII interfaces. From what I understand, these interfaces have LVDS logic levels. I am not use to seeing the termination scheme as recommended below. I thought the 100 ohm resistor should be near…
Matty
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sgmii auto negotiation - how long should this take?

I am working with LWIP - and an 1G marvell phy, m88e1111 - connected to a Microsemi SmartFusion 2 FPGA design using 10b8b (aka: TBI) interface. I'm doing something wrong with the auto negotiation and it's probably mostly me, I can't find things that…
user3696153
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How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?

The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics between them work as shown below? EC21 (SGMII pins)…
k051819
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SGMII to 100BASE-FX

I need to connect seventh port (SGMII) of KSZ9477S switch to AFBR5803AQZ optical transceiver (It's 100 Mbps). I wanted to use PHY with SGMII interface and fiber mode (VSC8658XHJ), but it's too expensive. I also found 88e1111 Marvell IC which should…
Andy
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SGMII, MDIO and link training

I am reading this document : https://www.nxp.com/webapp/Download?colCode=AN3869 I got this link from NXP support, but I did not get a precise answer to my questiosn and I would like to be sure : The NXP support told me that link training exists…
pierre123
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Does SGMII use MDIO?

I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, Basic Mode Control Register, ...) in the SGMII…
pierre123
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What is the standard common mode voltage of Media Dependent Interface MDI[0:3]± signals?

I am working on the selection RJ45 connector for MDI interface between PHY and the link-partner. I am planning to use this PHY for my SGMII interface application. From various online readings, I understood some RJ45 connectors can have CT (Center…
student7
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What is the SGMII differential peak to peak voltage?

I am trying to understand the SGMII Driver and Receiver DC specification. Here is the link to SGMII specification - SGMII.pdf I am studying. Table-1: Driver DC specification Table-2: Receiver DC specification Waveform created from above…
student7
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Serial Gigabit Media Independent Interface (SGMII) - 1.25 Gbps vs 1 Gbps?

What is the difference between 1.25 Gbps vs 1 Gbps SGMII signal data rate? My understanding is that 1.25 Gbps is the raw data rate and 1 Gbps is the actual data rate (After removing the headers and all other information attached to the data) Below…
student7
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Can I use an Ethernet switch IC without connecting to the mcu?

I'd like to add an unmanaged Ethernet switch IC to a board I am designing, but I have no free RGMII/SGMII/PCIe connection available on my MCU. The goal of this IC is just to save space/hassle (in the application I am targeting, I cannot afford to…
RH6
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