Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [setup]

28 questions
10
votes
5 answers

Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns. During the 6th positive edge, we see that the data (or X) is…
Zephyr
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4 answers

If the output of a D type flip-flop appears immediately on the clock edge, how can the previous output be used?

The way I understand it, the input value (D) of a D type flip-flop appears immediately on the output (Q) of a D type flip when triggered by a positive clock edge. If this is the case, then how can the value before the clock edge be used as an input…
Emil Eriksson
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4
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3 answers

Hooking up an LCD to Arduino Diagram

Has anyone got a really clear diagram of the way to link up a 16x2 LCD screen to an Arduino? Basically I have an LCD for which the back light is coming on, but I am not getting any words appearing on the screen. Which Pins should I be focusing on to…
mad_z
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3
votes
3 answers

AtTiny85 analog / digital pin configuration order in setup

Bug in compiler or what ever? Simplified circuitry there is 2 LEDs and 1 analog input. LED connected to pin PB1 lights very dim when output is high. It seems that output has been configured to high impedance mode. That happens if inside setup()…
Paavo Merilinna
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2
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1 answer

Need help setting up 7X6 Piranha LED Matrix with Arduino

I need help correctly getting my parts list for a 7X6 matrix that will be part of a electronic outdoor scoreboard. Here is my parts list so far but I am stump whether the arduino is powerful enough to power these LEDS in a matrix. 42 X Piranha…
Marcus Gollahon
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2
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3 answers

ultrasonic setup guide

Does anybody know of any online resources that go over the setup of driving ultrasonic transducers, as well as how to receive an ultrasonic echo, and pick it out (for rangefinding)? I found this article online...but it glosses over it almost too…
Nathan
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2
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4 answers

Flooring for home lab

I am setting up a home electronics lab for projects with my kids, currently ages 4 through 10. What type of flooring would work best? We will be doing art projects in the same room, so we need something easy to clean (no carpet). I would prefer…
Thomas Mueller
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Not seeing set_address packet using USBTrace

I'm currently exploring the wonderous world of the USB Stack. I'm using a PIC18F2550 and the USB IO example available at www.moty22.co.uk. The code works as expected, but when using USBTrace (or any other USB sniffer) I fail to see the set_address…
user32626
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1 answer

Why for setup check AND gates use rising edge, while OR gates use falling edge and vice versa for hold check in clock gating?

I have two questions on set_clock_gating_check SDC command. Why for setup check, AND, NAND gates use rising edge, while OR, NOR gates use falling edge ? Why for hold check, AND, NAND gate use falling edge, while OR, NOR gates use rising edge ?
kevin998x
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1 answer

Servo Motor set up

I want a servo motor to move/rotate a set distance and hold position (bear weight:which for my uses would be minimal) and then when power isn't applied/cut-off it drives back to original position. I'm trying to do this with a minimal amount of…
Brad Wilson
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2 answers

Significance of negative setup and hold time

What do you mean by negative setup and hold time i.e what happens if hold time is negative or setup time is negative. Does -ve setup or hold have any advantage ?
user22348
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1
vote
1 answer

Implementing input capture correctly on a PIC

I'm using a PIC16LF1827 with the XC8 compiler in MPLAB X. I need to store the time between pulses that are coming from an external moisture sensor. The length of time correlates to the measure of moisture. I'm utilizing input capture to capture the…
Osagie Igbeare
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2 answers

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
titan
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1
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2 answers

Setup and hold for positive edge flip flop cascaded with negative edge flip flop

I know the following for two positive edge triggered flip flops in cascade. Max(combinational logic delay) < Tclk_period + Tskew - Tsetup and Min(combinational logic delay) > Tskew - Thold But when I consider positive edge ff followed by negative…
Curious
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1 answer

How does setup and hold time affect the minimum clock period?

Do setup time and hold time of a register directly affect the minimum clock signal?
milly
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