A digital logic circuit containing feedback, in which outputs depend not only on present values of inputs but also on past values. Sequential logic is used to implement state. Contrast with "combinatorial logic", where outputs depend only on present values of inputs, and there is no feedback.
Questions tagged [sequential-logic]
95 questions
13
votes
3 answers
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
I have a piece of code in Verilog which needs to assign the value of shift register to an output register when the shifting has finished, and I want to reset the value of the shift register in the same clock cycle. Like the following:
[shift…
Martel
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9
votes
3 answers
How is the Q and Q' determined the first time in JK flip flop?
My background is in Computer Science, and this is my first time posting in electronics SE.
This is a circuit diagram of JK flip flop.
I don't understand how it works at the beginning, when the circuit is first on. In my understanding, Q and Q' does…
alu
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7
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5 answers
Why can't I make flip-flops in logic simulators?
I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates:
All the simulators I've tried give the same result. Either Q or Q' takes the state of the…
jozxyqk
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5
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2 answers
Does combinational and sequential logic correspond to some mathematical logic systems?
Is it correct that the functionalities of digital circuits are divided into combinational logic and sequential logic?
Is combinational logic the same thing as propositional logic in mathematical logic?
In automata theory, combinational logic…
Tim
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4
votes
2 answers
How can I output a sequence of bits using only simple discrete components?
My degree had given me some electrical engineering basics, and I like to keep studying it in my spare time. I would like to achieve something with electronics, which is why I am asking here instead of programming a microprocessor for the purpose.
A…
Daniel
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4
votes
2 answers
n bit shift register (Serial Out) in VHDL
I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low.
I've put a for loop to shift n times inside a process. My code is given…
Orange
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3
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Are there any "Both Rising Edge and Falling Edge Triggered" Shift Register?
I was designing this circuit in Logisim-evolution. In the book, it is mentioned that an n-bit multiplier would require n-clock cycles to work. I think this will be possible only when we have the shift register load during its rising edge, and make…
Vedanta Mohapatra
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3
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Question on timing diagram of a SR Latch with different gate delays
Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, #5)
module rs_latch(
input S,
input R,
output Q,
output Q_L
);
assign #10…
shinhong
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3
votes
1 answer
Flip-flop feedback timing problem
So this is my first question here.
I am reading this book, "Digital Electronics & Computer Design - By M.M. Mano". While I was reading the Sequential logic and flip-flops, I found this:
The feedback path between combinational circuit and memory…
Shubham
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3
votes
1 answer
Design a T flip flop and draw the asynchronous state diagram
I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when there is a transition from B to D in the given figure…
srinivas raman
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3
votes
0 answers
Motor Control - Counter design for the control circuit
I want to design a Johnson/ring counter circuit for control of my sr motor. Until now I have got this information, which I have tabulated in the following waveforms I am attaching for the reference:-
Now, I want to be able to run the motor at low…
mosfet
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2
votes
3 answers
Do we decide the output of a sequental circuit based on its present state or next state?
Suppose in a sequential circuit, we have an output which is based on the present state and the input, and the input of flip flops are based on the given input. When we change the input the output will change. Also the FF state will change from…
Emz
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votes
1 answer
Is Quine–McCluskey algorithm globally optimal or is there a better way for K-Map reduction?
A bit of context...
We are working on a project to convert FA (Finite Automata) to Digital Sequential Circuits and vice-versa.
In this process we came across a step: Reduction of Karnaugh (K-Maps).
Now, we are aware of the steps to be done when…
Dheeraj Lalwani
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2
votes
1 answer
Hold time constraint equation
I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint
Hold time constraint is defined as:
tccq + tcd ≥ thold
tccq is the…
NinjaTurtle
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2
votes
2 answers
How to know if a verilog code is sequential or combinational?
How to know if this piece of code is for a sequential or a combinational circuit?
James
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