Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [sdram]

SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a separate clock signal for moving commands and data to/from the device.

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SDRAM Termination Resistors: Are They Needed?

For a project I'm designing, I'm using an IS42s32800 (TSOP) SDRAM with an LPC1788 (QFP) microcontroller. On the PCB I have 4 layers with a ground plane right below the top signal layer and a VDD plane right above the bottom signal layer. Average…
ozg
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How can 8-bit processor support more than 256 bytes of RAM?

If a 32-bit processor can handle approximately 4 GiB of RAM (i.e. \$2^{32} = 4 294 967 296\$) bytes, why does my Arduino Mega 2560 have 8 KiB of SRAM, if being a 8-bit processor allows it to handle just 256 bytes (\$2^8\$)? Or am I reading the…
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Why was full page bursting removed when we moved to DDR

I'm interfacing with SDRAM on an FPGA and full page bursts are a godsend for streaming data. It's seems to be much, much more handy then a fixed burst size. I know it was removed when we moved to DDR. Does anyone know why the most useful burst mode…
John Smith
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Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller

I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's similar to how any standard SPI or I²C interface…
Polynomial
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SDRAM Prototype vs Production Woes

I have a design using an LPC1788 together with a SDRAM module from ISSI (IS42S32800D). This is a 32bit interface. I have routed this design out and had a prototype made with a PCB manufacturer that does 6 layer prototypes. The prototype PCB works…
James
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Choosing a SDRAM pcb layout

I'm working on a project with the quite new STM32F429 in LQFP208 package. I need to solder the first couple of prototype by myself for low budget reason. I choose this package so I could check myself if a problem is due to the routing/firmware or…
Leo
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SDRAM initialization issue (Freescale iMX31)

I'm trying to modify an existing init sequence (low level init of SDRAM) to accommodate a change in hardware configuration: an existing SDRAM on my iMX31 was replaced with a different size, otherwise same type/manufacturer/layout/pins/timings ..…
Peter Branforn
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How does random memory access of RAM work?

HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time. So, what makes RAM so special? How does random memory access work? (I know that DRAM is…
Dotcomio
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Freezing DRAM for forensics (coldboot)

I've known about the coldboot trick for a while, but have never really considered the physics behind it. I've read the paper, but it doesn't really cover why it works. How does physically cooling a stick of RAM to a very low temperature cause the…
Polynomial
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Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer frequency) is 200 MHz Internal clock rate of DDR memory is…
Sanjeev Kumar
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How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although VGA and SDRAM are already communicating with each…
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What is lead-in termination?

This term is mentioned in the Micron Application Note: Hardware Tips for Point-to-Point System Design on page 10 (...For signals with lead-in termination...), however I've been struggling to find out exactly what lead-in termination means. It's…
stanri
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Why not SRAM for FPGA in image processing?

I'm beginning with VHDL coding and I've done some basic image processing on my development board. I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM. For example, I'm using a FPGA dev board from TERASIC and it uses…
user17828
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What is pseudo-open-drain-logic?

DDR4 reportedly uses something called pseudo-open-drain-logic or PODL. How does it work?
joeforker
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Interfacing ADC Output with SDRAM

I am working on a design for a high-speed data acquisition device for a 10-bit ADC signal at 80 Msps. So far, it looks like most MCU boards are too slow to be able to route and store data and keep up with the high sampling rate. The latest board…
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