Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [sdc]

Synopsys Design Constraints (SDC) format is an industry standard to constrain integrated circuits for synthesis, timing, area, power etc.

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ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd like to ask the EE community for help with some…
FriendFX
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timing constraint for bus synchronizer circuits

I've a bus synchronizer circuit for passing a wide register across clock domains. I'll provide a simplified description, omitting asynchronous reset logic. The data is generated on one clock. Updates are many (at least a dozen) clock edges…
Ben Voigt
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Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by the clock divider to get two other clocks:…
Mitu Raj
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ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd like to ask the EE community for help with some…
FriendFX
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my external circuit has? What I hopefully understood…
SDwarfs
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock): always @(posedge…
fhw72
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Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. Still, when I have to code them in a sdc file I…
Giancarlo Sportelli
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How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this module are multidimensional arrays. For…
Matt B.
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Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: create_clock -name clk1 -period "150 MHz" [get_ports clk1] create_clock -name clk2 -period "150 MHz"…
Randomblue
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Constraining FPGA design on the lower level module

I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the optimization, marked as false paths. The lower level module…
Anonymous
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Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective clocks. The outputs of these 4 DFFs are connected to a…
cplusruss
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How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are "born", they are MUXed, and we call this generated…
Light
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Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: create_clock -name clk_i -period "157 MHz" [get_ports clk_i] I also know how to constrain input…
Randomblue
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Grouping input and output signals with the corresponding clock

In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and outputs. At the moment, my compiler (Quartus II) is not complaining when I mix I/O signals associated with clk1 with I/O signals…
Randomblue
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In an FPGA, is the input port delay related to the output port delay in the previous block?

Consider the following circuit in an FPGA: Let's say the output port O1 is constrained to have a min/max delay of 1 and 3 ns respectively. That means the circuit will be optimized for allowing a max. of 3 ns delay, after the Clk1 trigger, from F1/D…
Martel
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