Electrical Engineering Stack Exchange
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Questions tagged [sample-and-hold]

Anything related to sample and hold (S/H) circuits. S/H circuits are analog circuits whose purpose is that of sampling the instantaneous value of an analog signal and store that value for a predefined period of time. They are sort of analog memory circuits, and they are often employed as the first stage of analog to digital converter systems.

Anything related to sample and hold (S/H) circuits.

S/Hs are analog circuits whose purpose is that of sampling the instantaneous value of an analog signal and store that value for a predefined period of time. They are sort of analog memory circuits, and they are often employed as the first stage of analog to digital converter systems.

Usually a capacitor is used as an analog memory element in S/Hs to store a voltage level. Additional buffering circuitry and analog electronic switches are used to connect the capacitor either to the source signal (sampling phase) or to the load (holding phase) with suitable timing.

See also Wikipedia on sample and hold circuits.

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Exactly what is the role of the zero-order hold in a hybrid analog/digital sampled-data system?

I'll admit, I am asking this question rhetorically. I am curious what answers will come back out of this. If you choose to answer this, make sure you understand the Shannon-Nyquist sampling theorem well. Particularly reconstruction. Also be…
robert bristow-johnson
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How to achieve analog zero-drift sample and hold for hours?

This so-called "zero drift" opamp droops .001V/sec, at temp 85C with a 1 uF cap. If I'm reading the spec correctly, that's 3.6V/hour! http://www.ti.com/lit/ds/symlink/lf398-n.pdf Is there a method to store a low current V for up to about 5 hours…
Johny Radio
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How to sample and hold on very narrow pulse?

I am looking to construct a simple data logger to record the peak intensity from a flash strobe. When a flash is detected, the peak will be captured (ADC), time stamped and written to memory. The frequency at which these bursts of light arrive would…
Jason
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How do I prolong the reed switch output time

I put a reed switch ( https://en.wikipedia.org/wiki/Reed_switch ) on the handle of a measuring wheel (perambulator). The reed switch will be activated up to around 20 times per second (every 50 ms). The sampling rate on my data acquisition is 200 Hz…
phell
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DAC multiplexer glitch

UPDATE 20th May: Swapped the analog output regulator for an AZ1117-EH based on Peter Smith's suggestion, removed C1306, so now the 3.3VA output should be ok at least based on the datasheet. However, no significant improvement. See scope shots and…
Timo
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Track vs sample-and-hold

This is the output of both track-and-hold and sample-and-hold. But when I searched for its circuit I am getting the circuit I have shown below for both. So my question is: if the circuit for sample-and-hold and track-and-hold are the same then how…
Swap
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Op-Amp Sample and Hold Circuit Help

So, I'm trying to modify a sample and hold circuit from "The Forrest Mims Engineer's Notebook", that uses a 353 op-amp, so that it runs off of a single supply: I needed to add a 4.5V (1/2 supply voltage) offset to the inverting input, so that it…
Zack Frost
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Mosfet suggession for large drain current Sample Hold application

I'm using a MOSFET for a sample and hold circuit controlled by a microcontroller. I want to control the charging and discharging of a capacitor by a solar cell. For this I'd be using two MOSFETs. The solar cell can have a large area and can source…
Analon
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What is the difference between sampling time and sampling interval and sampling rate?

I understand that ADC sampling time is the ADC clock cycles for which the sample and hold capacitor is charged up to the channel input voltage. This is a configurable parameter and its value ranges between ns and us. Let's say I want to read ADC…
Vishwesh GM
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How to compare Matlab/Theory <=> Cadence: Switched-cap. Integrator: Mag & Phase

I tried to compare the simple switched-capacitor integrator below, between Cadence and Matlab (at the end acting as a simple loop-filter for a delta-sigma). I am stuck now on the point of how to compare the 2 results CORRECTLY, because of the…
bernd2700
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What will it happened when capacitance is almost the same as parasitic capacitance

I make a sample and hold (IC design),and it is combined with transmission gate and a 550fF capacitor,and my classmate told me that my capacitor is too small,almost the same as the parasitic capacitance,and also told me it may have some problem when…
Shine Sun
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Sample & Hold circuit not working for negative half cycle

I have made a Sample & Hold circuit using Multisim but after simulating oscilloscope showing sampled version of input waveform for positive half cycles only. I have used MOSFET as a switch with controlled voltage and its working fine. My question…
fahad shaikh
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What is the true measurement duration for each sample made by a DAQ?

When a data acquisition system digitizer (DAQ,) or analog-to-digital converter (ADC) samples a continuous signal, how can one estimate the true measurement duration of the sampling action? By true measurement duration I mean the window of time…
higgy
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Why is voltage across sampling capacitor going below 0V

I am trying to design a sample and hold circuit for a project, but I am not understanding some of the results for my current simulation. When my control signal (V1) is turned off, the voltage over the capacitor goes below zero as it discharges. Why…
uhhhhhhhelp
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Sample and hold & analog shift register

I have this circuit (see first picture.) it's an analog shift register where instead LF386 I use LF398H. This circuit must provide an hyperchaotic behavior for initial conditions x1(0) = l, x2(O) = O.l, and x3(O) = 0. The Sample & hold signal…
Julien
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