For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use.
Summary
RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
Features
A completely open ISA that is freely available to academia and industry.
A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.
An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.
An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.
Support for the revised 2008 IEEE-754 floating-point standard.
An ISA supporting extensive user-level ISA extensions and specialized variants.
32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.
An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.
Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.
A fully virtualizable ISA to ease hypervisor development.
An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.
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