Questions tagged [ripple-counter]
64 questions
6
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1 answer
Ripple counters versus synchronous--pros, cons, and power consumption
Substantial edit--note that David Kessner's answer was written in response to the original posting; view the edit history to see what he was responding to
From what I've read of digital design, there is a very strong tendency toward the use of…
supercat
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In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?
In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and…
user3001845
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Why ripple counter increments on each 8th pulse
I have connected the ripple counter CD4020 to an Atmega328, which sends a 50ms (low logic level) pulse to the CD4020's input each second and monitors all of its 12 outputs.
However instead of incrementing the output on each pulse, the CD4020's…
Alexander
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3
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74190 counter problem
So, I got my 74190 counter shows number like this
9-8-7-6-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0 and so on.
My questions:
What can I do to change the output count down into 5-4-3-2-1-0-5-4-3-2-1-0 and so on?
When it changes 0 into 5 it…
Evangelina Tessia P
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3
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2 answers
Ripple counter, reset problem (J-K flip flop counter)
I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010).
The thing is it does not reset but goes to 4 (0100) due to the reset on my second flip-flop (it sends a…
E. Villalobos G.
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3
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2 answers
Issues implementing an up/down counter
I am trying to understand how to implement up/down binary ripple counter.
Basically, I have a bunch of D-flipflops, and connect clk of next flipflop to ether Q or Q'.
So, if I want to change direction of counting, I just switch all clk multiplexors…
BarsMonster
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Are there different versions of 4060 counter IC available?
I was searching for datasheet of 4060 IC (my part number is HEF4060BT, made by NXP) and found different versions with different stages.
Is this just a vast typo in labeling pins in datasheets or some claimed 14-stage counter ICs are actually…
Bikay
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2
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1 answer
Modulus 5 counter
I'm trying to build a Modulus 5 counter using TTL in Multisim that will count 0-4 and reset on 5. From the K-map I got Q2' + Q0' and using that...
Strobe = Q2'+Q0'
Strobe''= (Q2'+Q0')''
= (Q2'*Q0')''
Strobe = (Q2Q0)'
' = not.
I've built the…
Licentia
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Why do we reset/clear at 1010 (10) when designing a BCD Ripple Counter
Shouldn't we reset at 9, I believe that a decade counter goes as follows '0->1->2->3...->8->9->0" or at least that's how its done for synchronous BCD counters.
Essam
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2
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Active high-active low for preset
In a FF when clear is 0, output is also 0.So what should it be considered as ? Active low or high clear? If it active low doesn't it mean that output should be 1 ?
Siddharth
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2
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3 answers
Propagation delay in asynchronous counter
Are the ripple counters useful in real life?
I know, for example, if we set an up counter with 3 FFs, CBA. Followings are the block and the waveform diagram:
After the count 001, it will appear 000 (the 2nd CLK period), which makes the operation…
W.Joe
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2
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Issues with the initial state of a 7447N driver to BCD in a MOD 56 ripple counter
I'm currently doing an assignment for school where I have to construct a MOD-56 BCD ripple counter using JK Flip Flops. This requires 2 BCD displays and 7447N drivers to interpret the bits from the flip flops as the clock cycles. After finally…
The Progenitor
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Why use JK Flip Flops in syncronous/asyncronous binary counters rather than D flip flops?
Everywhere I encounter either asyncronous (ripple counter) binary counters or syncronous ones, the application uses JK flip flops with the J and K inputs tied together, such as described here:
From my understanding this reduces the functionality of…
Alex
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2
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2 answers
what is meant by Divide by N and Modulo(N) in counters?
I am trying to understand counters. Can anyone of you clarify me about terms (Divide by N) and Modulo(N) used in counter? What exactly it means?
Ranjan
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Asynchronous Cascaded Counters Problem!
What is the Frequency and Duty cycle and of the waveform at Z (say if input clock frequency is 1.5Khz)
My Understanding:
Two negative edge triggered MOD 12 counters cascaded and reset when the upper counter is at 0110 and lower counter is at…
Ashik Anuvar
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