Questions tagged [race-condition]
17 questions
13
votes
5 answers
Why does the race hazard theorem work?
So for those who don't know, the race hazard theorem (RHT) states that:
A x B + A' x C = A x B + A' x C + B x C
I understand the other part of the RHT, about time delays and such, but I don't understand why the logic statement above should be true,…
Alex Robinson
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Can a register remove the race condition in this case?
My book has this example of a race condtion:
The race condition is: If D and CLK is 1, and CLK goes to zero, then we want the output Q to remain 1, however if the inverter is slow compared to the other logic gates then the output may be…
user394334
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3 answers
Does the master-slave JK flip-flop really solve the race condition?
The master-slave JK flip-flop is said to solve the problem of racing, as per many online resources that I've referred to.
However, let's say that the initial state of the flip-flop is CLK = 0, J = 0, K = 0 and Q = 0.
Now, K is turned to 1 while CLK…
Kushagr Jaiswal
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2
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2 answers
Is there possibility for a race condition in the following circuit?
On this wikipedia page, there is an example of a circuit which implements a D latch using NAND gates :
Let's say the flip flop is initialized correctly (eg : Q = 0 and !Q = 1).
If D = 1 and E = 0, the right part (which is, AFAIK, a SR latch) will…
tigrou
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2
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2 answers
Karnaugh Map race conditions with don't cares
Karnaugh maps show race conditions as adjacent minterms that are not covered in the same implicand. Take the following example:
We have race conditions when moving from the blue implicand to the green one, and the blue implicand to the red one…
jeanluc
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vote
1 answer
How do I figure out if my Verilog code output was generated out of race condition?
Apart from physical observation, is there a way to know if my code will undergo a race condition?
For example, the following code has a race condition because both initial blocks will start at 0 simulation time in the active region, which is…
Killjoy
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4 answers
When can the output of any flip flop (e.g., JK FF) be indeterminate?
I came across following problem:
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
A. Q = 0, Q' = 1
B. Q = 1, Q' = 0
C. Q = 1, Q' = 1
D. Indeterminate states
I (wrongly)…
RajS
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1 answer
Why does this Verilog testbench not undergo a race condition?
This is the testbench in question:
module tb;
reg a,b;
initial begin
$display("a=%0d | b=%0d", a,b);
a = 1;
b = 0;
a <= b;
b <= a;
end
endmodule
Ignoring the evaluation of RHS of non-blocking…
Killjoy
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0
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1 answer
How do y1 and y2 take on two different values here? Can someone please explain the order of assignments?
The following code snippet is an example from a SNUG 2000 paper that explains race conditions. The explanation for the race condition is given below, but I do not understand it. How is y1 and y2 = 1 if the first always block executes first? Or 0 if…
penguin99
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Lattice ICE40-LP1K 84-QFN SPI Flash Programming
I'm using ICE40-16-WLCSP-Eval-Kit as a reference design for the Lattice ICE40-LP1K 84-QFN which I'm going to use in the motherboard I'm designing.
I did a little experiment with ICE40-16-WLCSP where I externally programmed the SPI Flash and saw that…
Firas Abd El Gani
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0
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2 answers
Will a synchronous circuit have a race condition if not all inputs arrive before the clock rising edge?
Suppose that the circuit has several inputs from an external circuit which do not have an effect until the clock next rise edge due to using synchronous flip-flops. If the external circuit sends several inputs and because there is a different…
dev65
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Is more clock speed means higher risk to circuit can have race condition
It is a very simple question but it made me think. I have been working on finite state machines. I came to topic of finite state machines from combination circuits. In the book it says that sequential circuits which uses register with same clock…
asimtot
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Latching Priority Encoder, circuit works but I don't trust it
I added a schematic even though the question is actually too simple for it. The datasheets for the devices are likely to be more revealing.
The circuit is super simple. I have a 74HC148 priority encoder. I attach its encoded outputs (A0..A2) to…
DarylK
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0
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1 answer
Delaying clock pulses without adding (much) extra circuitry (CMOS)
I have a counter (74HC193) counting up with Qn outputs being decoded by a demultiplexer (74HC138). My clock pulses (CP) are no less than 100 microseconds long and the interval between them is always greater than that. The counter counts on the…
DarylK
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0
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1 answer
Interaction beween DMA transmission complete and peripheral interrupts
I have two related questions regarding using DMA with an STM32 chip. I'm using STM32F031C6, but the answer should apply to other models.
I setup the USART to issue a character match interrupt. I'm using DMA to read the characters from the USART. …
Dan Sandberg
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