Questions tagged [questasim]
15 questions
4
votes
1 answer
VHDL: Non-locally static choice warning
I have the following code:
constant HALF_RANGE: unsigned(RANGE_WIDTH-1 downto 0) := (RANGE_WIDTH-1 => '1', others=>'0');
where RANGE_WIDTH is a generic of type integer. It does exactly what is should: Generate a constant where the first bit is 1…
Botnic
- 2,245
- 2
- 19
- 33
2
votes
1 answer
How to set QuestaSim/ModelSim to print time value in arbitrary unit?
Here is the code:
wait for 1 ns;
print("x is checked, last changed at " & time'image(x'last_event));
wait for 10 ns;
print("x is checked, last changed at " & time'image(x'last_event));
wait for 100 ns;
print("x is checked, last changed at " &…
gyuunyuu
- 1,933
- 7
- 31
2
votes
1 answer
Error with Assert statement in Verilog
I have the following assert statement in a for loop, which is within a generate block:
34 assert ((a[j] == 1'b1) || (a[j] == 1'b0))
35 else $error("Input 'a[" + j + "]' is not a digital logic value");
When I try to compile, I get the following…
Lakshya Goyal
- 157
- 9
1
vote
1 answer
Bad default binding, component port not on entity
I am trying to write a testbench for a basic component, but I am getting an error saying:
bad default binding for component instance (component port not on
entity)
I have tried recompiling multiple times in both quartus and questa, have restarted…
Baddioes
- 13
- 2
1
vote
1 answer
Multiple wire type objects declaration Verilog
I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring inputs)? When can I use the same line and declare…
SM32
- 366
- 2
- 12
1
vote
2 answers
ModelSim: Why can't I see generics in simulation?
When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. However, generics are nowhere to be seen. How do I…
quantum231
- 11,218
- 24
- 99
- 192
0
votes
1 answer
How to randomize the seed-number in Modelsim?
In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number.
I was wondering if Modelsim has the similar automatic…
Taher Anaya
- 3
- 1
0
votes
1 answer
For QuestaSim, what's the difference between vsim.exe and vsimk.exe?
For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe?
for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, some Windows computers require me to use…
pico
- 183
- 1
- 1
- 9
0
votes
0 answers
Syntax error in SystemVerilog based UVM testbench
I have been getting the following syntax error on compilation-
** Error: (vlog-13069) ** while parsing file included at testbench.sv(2)
** while parsing file included at mypackage.sv(11)
** at dpram_if.sv(1): near "dpram_if": syntax error,…
em.
- 9
- 3
0
votes
2 answers
Is there a way to define enumeration for certain signals after simulation?
I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To look at strings instead of bit streams).
Is there…
ECEVLSI
- 29
- 1
- 8
0
votes
1 answer
VHDL: reading integers from a text file, storing them in array, and writing in text format again
In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like,
0000
0001
0005
3864
2290
1234
.
.
.
0002
0004
0006
4532
3457
.
.
.
My aim here is to read the text file, store first few…
rooter
- 3
- 1
- 3
0
votes
1 answer
A question about randomization in verilog
I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog doesn't seem to be working and tried typing…
eric yau
- 9
- 1
0
votes
1 answer
Is there a way to suppress the output when compiling multiple vhd files except for errors?
I have a compilation script I run before simulating on QuestaSim 10.7:
vcom -vhdl -2008 my_lib -check_synthesis src/mux.vhd
vcom -vhdl -2008 my_lib -check_snythesis src/clockdivdeby2.vhd
...
I receive an output on terminal as follows:
vcom -vhdl…
Cit5
- 235
- 2
- 9
0
votes
1 answer
"Numeric value exceeds 32-bit capacity" error in QuestaSim
In the testbench for a SystemVerilog module, I have the following array declaration and initialization:
real testVals [][] = '{
'{1.5, 1.5},
'{2.0, 3.0},
'{0.0, 0.0},
'{-1.5, 1.5},
'{-1.5, 4.0},
'{-1.5, 3.0},
'{-1.5,…
skrrgwasme
- 828
- 8
- 32
-1
votes
1 answer
Simulation only code and Synthesis only code in QuestaSim
Pragma exist to tell the synthesis tool to ignore lines or blocks of code, using this:
-- synthesis translate_off
... code to ignore
-- synthesis translate on
But are there pragma that can be used to tell the simulator to ignore certain lines or…
gyuunyuu
- 1,933
- 7
- 31