Questions tagged [quartus-ii]

Altera Quartus is a programmable logic device design software from Altera.

Quartus II (known as Quartus Prime since version 15) is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The latest version is 16.0.

129 questions

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Altera FPGA I/O weak pull ups

In altera FPGA documentation they make reference to a "I/O weak pullup" functionality. I would like to use internal weak pull up instead of external pullups , avoiding a PCB modification. It seems is possible to activate weak pull up for an I/O in…

asked Jul 27 '16 at 12:45

Cristian Mardones

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5 answers

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs bits than there are physical pins, so Quartus II…

fpga verilog quartus-ii timing-analysis

asked Nov 29 '13 at 11:42

Randomblue

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Free linting tool for Verilog

Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.

fpga verilog xilinx programmable-logic quartus-ii

asked Jun 15 '13 at 12:49

Osaid

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4 answers

Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree (or whatever), and if I send it 20 pulses, the…

fpga vhdl stepper-motor intel-fpga quartus-ii

asked Jul 31 '13 at 14:26

Engineero

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3 answers

How to define a clock in Quartus II?

I have this piece of code here: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity first is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); result : out STD_LOGIC_VECTOR(3 downto…

fpga vhdl intel-fpga quartus-ii

asked Apr 19 '15 at 21:25

gilianzz

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2 answers

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any worst-case paths in the TimeQuest report. How can I generate timing worst-case paths in…

fpga intel-fpga quartus-ii

asked Aug 19 '13 at 12:18

Randomblue

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FPGA encoder counter running away randomly

I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code thanks to the StackExchange community, but now I am…

fpga intel-fpga encoder quartus-ii quadrature

asked Jul 31 '13 at 14:51

Engineero

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2 answers

Quartus II: Customise compiler messages

I am working with the Altera Quartus II compiler for my Cyclone IV. I am not happy with what is considered Info, Warning, Error, etc. For example, inferred latches are Info, but I want them as Warning. Parallel compilation disabled is a Warning, but…

fpga intel-fpga quartus-ii

asked Sep 18 '12 at 19:40

Randomblue

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What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be synthesized? How does one see fixed point…

vhdl quartus-ii modelsim binary

asked Nov 23 '16 at 14:28

quantum231

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How to speed up Modelsim simulation

How can I get Modelsim to run faster for simulation rather than something in the picosecond range (time interval)? Are there any other methods for speeding up simulation? It takes 45 minutes to get to 1ms as of now. I want the simulation to run…

fpga vhdl quartus-ii modelsim

asked Jun 06 '16 at 11:35

Alex Krish

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2 answers

Quartus: What is the purpose to "register output port" when RAM or ROM megawizard?

The RAM and ROM megawizards in Altera Quartus II give the following option in the GUI "Which ports should be registered?" The options vary but are: ‘data’, ‘wraddress’, and ‘wren’ write input ports ‘raddress’ and ‘rden’ read input port Read output…

quartus-ii rom

asked Jan 12 '16 at 20:41

quantum231

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Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which clock should be used for the Avalon-MM interface. I…

intel-fpga quartus-ii

asked Apr 26 '15 at 10:10

TEMLIB

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Reason behind Altera's divide functions pipeline delay?

In Quartus II, the standard lpm_divide function has a parameter PIPELINE_DELAY. The default value is floor(WIDTH_Q div 2) - where WIDTH_Q := width of the quotient in bits. I'm curious why this is a parameter there for the user to change (rather than…

fpga quartus-ii quartus

asked Mar 27 '14 at 15:31

OJFord

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3 answers

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only output another pulse the next time ready goes HIGH…

fpga verilog intel-fpga quartus-ii system-verilog

asked Mar 12 '14 at 11:01

geft

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1 answer

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks correct in terms of functionality. However, the…

verilog intel-fpga quartus-ii synthesis system-verilog

asked Mar 10 '14 at 15:35

geft

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