Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. I have been recently alerted that FPGA may yield…
Fraïssé
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Why do FPGA projects always take the same amount of time to compile?

With software, when we compile the project for first time it may take a while but afterwards, it does not take so long anymore. If we change a single file in the project, everything does not need to be compiled again. This does not seem to hold true…
gyuunyuu
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FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless no matter how many characters I send with the…
Rehin
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Is using floor plan tool during FPGA design ever actually useful or required?

I have used Intel Quartus and Microsemi Libero. Both of these tools contain a method whereby we are able to view the floorplan of the FPGA, hover the mouse around to see what parts of netlist have been mapped to different locations on the FPGA…
gyuunyuu
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Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?

My Altera Quartus builds show this warning... Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for…
JimFred
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Altera FPGA I/O weak pull ups

In altera FPGA documentation they make reference to a "I/O weak pullup" functionality. I would like to use internal weak pull up instead of external pullups , avoiding a PCB modification. It seems is possible to activate weak pull up for an I/O in…
Cristian Mardones
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Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. The rapid-recompile button is always grayed out, I…
Voltage Spike
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock): always @(posedge…
fhw72
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How do I generate a schematic block diagram from Verilog with Quartus Prime?

The answers to this question say that Altera Quartus will generate block diagrams from Verilog files. I'm a user of Quartus Prime Lite Edition. How do I generate block diagrams?
Ellen Spertus
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Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, constraining the timing of all clocks and…
bieux
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Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what affects it, but it seems that nothing works. I have…
user2704336
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Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the same design twice ( given the same software version ) ?
shaiko
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Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one route it to a block. Usually I create a custom…
Voltage Spike
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Reason behind Altera's divide functions pipeline delay?

In Quartus II, the standard lpm_divide function has a parameter PIPELINE_DELAY. The default value is floor(WIDTH_Q div 2) - where WIDTH_Q := width of the quotient in bits. I'm curious why this is a parameter there for the user to change (rather than…
OJFord
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Constraining FPGA design on the lower level module

I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the optimization, marked as false paths. The lower level module…
Anonymous
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