Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [power-sequencing]

Power sequencing involves circuits with multiple power rails to analog or digital electronics. Upon powering a circuit the rails must be sequenced with time to reach their designed voltages to ensure proper device operation. This is most common with digital devices such as FPGA's or Processors with multiple voltage rails and high current loads. If the rails are sequenced wrong the device might power on in an undetermined state and may not function properly

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Can I ignore the Power up Sequence

I am designing a board where the datasheet suggests a power up sequence. Basically, the VDD_PLL should be turned on first, after 100us, the VAA should be turned on, followed by the internal supply and then the VDD_IO. Current I am using the AMS1117…
red car
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Power sequencing in FPGAs and MCUs

I have a question about power sequencing requested by FPGA/MCU datasheets. I always see in datasheets that a particular power supply input must reach a voltage level before another power supply input (for example Vcore before Vio). But every time I…
Yaro
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Interview FPGA question about what I would power first

I have been asked this question in an interview, and I wondered what the correct answer was and why. What should you power on first in an FPGA? Is it the Core Logic, I/O blocks, or the memory?
Zarif Rahman
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LDO in split supply behaving incorrectly when power supply sequence is "wrong"

I'm powering an op-amp (OPA657) in transimpedance configuration. I externally supply ±15V, with LDOs to drop to ±5V; here I omit the feedback loop for simplicity: When I turn on the negative rail (-15V) first, my positive-regulating LDO…
user2022444
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Why do ICs need a specific power down sequence?

When powering down a board, for ICs that have multiple supply voltage rails, why do they need a specific power down sequence? Typically in complex motherboards, there is a CPLD doing the job of this power down sequencing. Why don't we just pull…
Neil Dey
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Power up sequence

I am designing hardware where a specific power up sequence is needed. The Vdd_33 should come 10 µs after vdd_18. I have LDOs for these supplies. One option is to control the power distribution with the CPU but this would require either a MOSFET or…
Ktc
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Using Power Good pins for sequencing

I'm trying to figure out a way to use the Power Good outputs of several stages of voltage regulators to sequence and monitor a board powering several FPGAs. I've done this easily before with a microcontroller, but this is not allowed (!) in this…
Dejvid_no1
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Power sequence solution with limited board real estate

I am designing a power supply using the LTM4639 part. VIN (3.3. V) needs to be sequenced before the bias input (5 V) in order for soft start to work. However there is no fixed timing relationship between both sources in my design and I am running…
JackOTrade
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What's the reason for power-down sequencing in a SOC? Can you damage it in some way?

Power-on sequencing I understand. But why do power-off sequencing? I could understand if you had to do something before power died, or maybe you just wanted to shutdown I/O before core so that no crazy pins are toggled while you're on your way…
confused
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Power supply for FPGA

I have a Spartan 6 FPGA (XC6SLX9-2TQG144) and I'm designing a power supply for it. Let's assume that I will utilize all of its logic (very possible) and I want to clock it as fast as possible (around 350MHz). How can I estimate the power (number of…
zupazt3
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Any good method for the power down sequence?

In my circuit, +12V would be supplied by an external power source. After two regulators, two more voltage sources (+5V and +3.3V) would be produced and supply power to the AD7682 ADC. Because of the maximum rating limit of ad7682, 3.3V needs to be…
billyzhao
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LTM8073 integrated DC-DC buck converter issues

I have a board with two LTM8073 "silent switcher µModule regulators" by Analog Devices/Linear Technology being used to provide two separate power supplies. This is a 10-layer dual-sided board that was put together by a very experienced PCB…
Edgar Brown
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TFT LCD voltages and sequencing

In the recent project I am working on I want to connect a TFT LCD to ESP32-S3. I would be using the LCD hardware interface of ESP32, so I only need to take proper care of display power management. The model I have currently, is ZJ050NA-08C by…
fafaldo
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Power sequencing two +5V rails without a voltage drop

I'm new to power sequencing and wanting input on the best way to solve this problem. I have two separate +5V rails on my PCB coming from a rectified wall source and USB. Due to back powering issues, I only want +5V on each rail when both power…
Nathan B.
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Schematic review: prioritized power ORing

I am in the process of designing a circuit which will allow me to safely OR two power supplies. Constraints: 5V up to 5A from Vin_hi_prio up to 2A from Vin_low_prio Both come from the same PSU but through different routes Vin_hi_pro should be…
jaskij
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