Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [power-integrity]

21 questions
10
votes
6 answers

How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of current, will it be separated between these four…
Selva97
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8
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2 answers

Is one big via better than multiple small vias when changing power traces and ground between layers?

I'm confused about the via placement in power traces either to change layers as part of routing the main supply or to get to component pins from a layer different to where the power trace is located, and from components such as decoupling caps to…
m4l490n
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3
votes
1 answer

Track vs Via impact on power integrity

This question is from perspective of power integrity and not signal integrity. Power can be delivered from VRM to an IC using copper tracks and vias. Both of these have inductance and we want to minimize inductance. One to do this is to use…
quantum231
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3
votes
1 answer

Bulk capacitance near a processor affecting converter transient response

Here is my question: why do manufacturers of processors and FPGAs prescribe adding hundreds or thousands of microfarads of bulk capacitance next to their part? The IGLOO2, for example, recommends a grand total of 1090uF of bulk cap on its core power…
moriarti
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2
votes
1 answer

Connecting '-' terminal of the power supply to the earth GND

I've already asked a similar question in the past, but I want to make sure I understood things correctly. Attached is the current lab setup for my chip testing. The green square represents the main PCB board, and the little blue square represents…
Emm386
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2
votes
2 answers

Using main board power supply rails in add-on boards

Many boards come with board-board connectors that can be used to connect another PCB to add new functionality. There are many examples of this. Some that come to mind are Arduino shield, Click boards™, mikroBUS™, PMOD, HSMC, FMC among others. Some…
quantum231
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1 answer

What is difference between IBIS model and IBIS-AMI model and what are specific application of these two models?

I am working on PCIe 3.0 compliance testing from signal integrity and power integrity point of view. I would like to understand the difference between IBIS and IBIS-AMI model and which model is good for my simulation? These models are used in…
Anil Pandey
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1
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S parameter model of the capacitor

For same capacitor, there is no s-parameter model, so can we use the model from other manufacturer of the same spec. Eg: Caps with model - C0603C104K5RACTU - KEMET - Cap, Cer-X7R, 0.1uF, 50V, 10%, 0603 without model - 0603B104K500CT - Walsin -…
Selva97
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1
vote
0 answers

EMI EMC analysis of converters

Probably not the best place to ask this question, I'll remove it if not received well. I am trying to perform EMI/EMC analysis of my resonant buck converter PCB. I tried to use ANSYS SIwave for this, but I'm not able to find much documentation on it…
SM32
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1
vote
1 answer

estimate (measure) parasitic inductance of a lead frame of a chip package

UPDATE: How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package? This parameter is very important at high frequencies (1GHz and more) because it affects power integrity. E.g. 10 mA current at 1 GHz…
Sergei Gorbikov
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1 answer

FPGA decoupling capacitors

FPGAs have among the largest packages and the most voltage rails. This is especially true of the high end devices e.g Stratix, Virtex Ultrascale+ e.t.c. This means a whole lot of decoupling capacitors. Decoupling capacitors is one way to improve the…
quantum231
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Shall I connect '-' terminal of power supply to earth GND (green terminal)?

Attached is the current lab setup for my chip testing. The green square represents the main PCB board, and little blue square represents the chip. The chip needs separate VDD voltage for its analog and digital circuits, but their ground is tied on…
Emm386
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0
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1 answer

Is there any benefit of the power plane capacitance to PDN?

PWR and GND plane make a capacitor with the dielectic in between them. The closer the two planes are physically, the higher the electrical coupling and thus the capacitance between them. Power delivery network relies a lot on decoupling capacitors…
quantum231
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What is Cross Impedance spec in PDN?

What is cross impedance spec in PDN? How do we define the cross impedance spec for a given power rail?
Ananthesh Acharya
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Signal integrity, number of DFE taps?

How do we determine how many DFE taps are required for a particular channel? Also, is there a relationship between the number of taps and the frequency?
ziA
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