PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
Questions tagged [pll]
381 questions
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What is the difference between a PLL and a DLL?
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what applications they might be used, the comparison between…
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PLL - why compare phases not frequencies
I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to compare phases, and NOT just compare…
mbes
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Why is the MCU clock out waveform sinusoidal and not square pulse
I got a new oscilloscope :) (proud amateur moment)
I am trying to visualize the internal clock of a STM32G431RBT6 MCU. So I built an example program given by the vendor which provides the MCU clock output on a GPIO pin. I connected my Rigol DS2202A…
anirudhan
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How can over 24 GHz communication be possible?
I read the article Google wants the US' wireless spectrum for balloon-based Internet. It says to use over 24 GHz frequency spectrum for communication.
Is it ever possible to generate that high frequency by using piezoelectric crystals? Or are they…
tcak
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What is the purpose of PLL in a general microcontroller
An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a PLL? and All About Circuit - What exactly is a…
KMC
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How do processors control their clock speed?
I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power.
For something like a desktop processor where the clock speed can be changed to any desired frequency…
user160063
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What is the difference between first order, second order and third order phase locked loops?
What does PLL order represent?
What are the disadvantages in order 1 & 2 PLL comprared to order 3?
How to choose the pll type for an application like QPSK demodulator?
Aparna B
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Why do we need phase-locked loops?
I'm very confused about why we need phase-locked loops.
On ScienceDirect.com, it reads:
Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit is to synchronize an output oscillator signal…
user3094631
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Using PLLs inside FPGAs
A document states that:
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
You can use the PLLs as follows:
Zero-delay buffer
Jitter…
gyuunyuu
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Why do frequency synthesizers often use N/N+1 prescalers?
Frequency synthesizers, like Analog's ADF411x often have prescalers in their PLL which divide by 16/17, 32/33 or 64/65? What's the 2^N+1 value used for?
stevenvh
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All Digital Phase Lock Loop
I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals is ~0.1-1% of the clock. I can't use the onboard…
crasic
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Why is there a PLL in CPU?
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
Jonas Daverio
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How do I drive 14.3Mhz clock input from 10MHz?
I intend to use an IC which requires 14.3MHz clock input, but want to drive it from a stable 10MHz source - derived from GPS. How do I turn the 10MHz clock into the 14.3MHz that the IC requires?
Mark
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How does a PLL inside a FPGA work?
I have used Altera FPGAs from last year and I would like to know how the PLLs inside works.
Mainly, really have any kind of analog circuitry inside in order to measure phase-offset between VCO and external signal?
This pretty pieces are so reliable…
Jairo Andres Velasco Romero
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Ways to observe clock signal of an STM32 MCU
Is there a nice way to be able to observe the clock signal in an oscilloscope to validate my settings for clock speed? After setting it to 168 MHz with PLL for an STM32F407VGT6 MCU let's say.
muyustan
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