PlanAhead is Xilinx's replacement for their ISE FPGA design software.
Questions tagged [planahead]
8 questions
17
votes
4 answers
List of Xilinx file suffixes (for ISE)
I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead
Some of the information they have provide is the…
Brian Carlton
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What files/directories are needed to recreate a Xilinx PlanAhead project?
I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and output files.
Yes, I did ask Xilinx in a WebCase,…
Brian Carlton
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2
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1 answer
Which is the best way to version control Xilinx PlanAhead projects?
Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead.
This ISE projects are under version control in a SubVersion repository, so I need to define the…
David Quiñones
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Partial Reconfiguration in FPGAs
I have been doing a project involving partial reconfiguration of a FPGA for some time now. I am having trouble understanding what is meant by terms like 'partial bit file', 'bitstream' etc. How can a .bit file be partial? Also, I know Xilinx…
mac93
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This design does not fit into the number of slices available in this device
Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum code 4 times. Is there any tweek to merge LUTs and…
Pradeep S
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Obtaining timing score of a implementation run with a PlanAhead TCL script
In a PlanAhead TCL script, I need to know the timing score of a completed implementation run.
I have found an old way to do this from 2012. The solution is read directly the PAR report file.
In Vivado exist the TNS property that can be read directly…
David Quiñones
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0
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1 answer
Why Differential Standards do not exist in FPGA PlanAhead?
I have never used differential I/Os in FPGA ( XC3S400). I always use PlanAhead for pin planning .When I click on a specific pin, it has all single ended standards but none of the differential standards exist ( as LVDS-25 , DIFFxxx, ...). When I try…
Aug
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PlanAhead 14.7 multiple runs issues
My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic parameters to customize each synthesis to a…
David Quiñones
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