Questions tagged [pipeline]
23 questions
4
votes
1 answer
Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file that cannot be read and written simultaneously, we…
Lei Gao
- 113
- 1
- 6
3
votes
2 answers
How to pipeline an algorithm that not only has latency but also relies on feedback of the previous run?
Trapped in this problem for several days, I feel I can't think of a proper solution on myself. The problem is as below.
Say, a source-input is streaming a sequence of A, denoted by A0, A1, A2, ..., Ai, ..., An.
Now I'd like to do some action on A,…
xc wang
- 167
- 5
3
votes
1 answer
With what stage of the branch instruction does the IF stage executes if the branch is taken?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong.
Consider an instruction pipeline with five stages without any…
Anshul Gupta
- 385
- 3
- 12
2
votes
2 answers
Pipelining digital logic with feedback
EDIT:
Unfortunately, the example below was poorly chosen. Several people correctly pointed out that x2 is just a bit shift and doesn't actually require a multiplication. I'm aware of this but I overlooked it when attempting to devise a sufficiently…
MattHusz
- 1,033
- 9
- 15
2
votes
1 answer
Doubt in pipelining forwarding in MIPS
I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google
I have a doubt in part b of problem 2 where we are asked How many cycles will it…
nmnsharma007
- 123
- 5
1
vote
2 answers
FSM vs Pipeline
I am new to the world of HDL. I am currently working on implementing AES in Verilog code.
I manage the flow of my logic using varying FSMs. Given this approach I currently have to wait for the first block to finish processing before inputting the…
ChrisMcNeill
- 11
- 2
1
vote
0 answers
How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question here question number 5.
Consider an instruction…
Anshul Gupta
- 385
- 3
- 12
1
vote
0 answers
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7, R5, R6}…
Abhishek Ghosh
- 155
- 8
1
vote
1 answer
Throughput increase/decrease by how much percent
I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me?
The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350
picoseconds. The second and third stages are merged into a…
Anshul Gupta
- 385
- 3
- 12
0
votes
0 answers
RISCV pipeline implementation, general questions
Good day,
I am currently working on a RISCV32 core for a personal project in order to learn FPGA developpement.
I have fully implemented all the base instruction set instructions and each of them is executed in a single clock cycle, with some clever…
Vladouch
- 11
0
votes
1 answer
Why do we need stalls even if branches can be determined?
I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (Chapter 4.6) that has me puzzled:
Let's assume…
Prithvidiamond
- 103
- 2
0
votes
1 answer
Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
Nidhi
- 87
- 2
- 11
0
votes
1 answer
classic RISC pipeline: Why does memory access stage comes before register file write back?
Here are two confusions:
Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers?
It seems that once the execution is done by the ALU, the register write back…
lousycoder
- 455
- 3
- 11
0
votes
1 answer
How does CPU control implement pipeline stall
The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.
How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during instruction fetch? Specifically,
Does the cache…
Oliver Young
- 123
- 4
0
votes
1 answer
where to place registers in VHDL modules
I'm a software guy by trade and I have been dabbling in digital design on FPGA using the open source toolchain. I have made a few designs and generally understand how the handle verilog and VHDL.
One of the things I'm wondering is not really a black…
John Smith
- 193
- 10