Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [pci]

The Peripheral Component Interface (PCI), a parallel master-slave bus, was the dominant bus to connect computer peripheral cards in personal computers and servers. It was mostly superseeded by the very different PCI express (PCIe) interface.

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What are the advantages of this gold finger shape?

Some PCBs, like the PCI card specification have gold fingers which start very narrow near the bottom edge, and gain their usual width much higher, where the actual contact is expected to be made. What is the advantage of having the narrow part? Why…
akwky
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Why is a PCI card treated as two loads on the PCI bus?

In PCI bus introduction materials, especially when talking about the load capacity of the PCI bus, it's often stated that a PCI card inserted into the PCI slot is actually acting as two loads on the bus, one is the card itself, the other is the slot…
bruin
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Backwards compatibility of PCIe AC coupling capacitors

The PCIe base spec mentions that platforms operating only at 2.5GT/s or 5GT/s may use AC coupling capacitors in the 75nF-265nF and that platforms supporting 8GT/s and above must use 176nF-265nF. However, PCIe uses low frequency pulses to detect the…
user2005848
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How are BAR registers handled between end points in PCI Express?

I have a question related to the PCI Express protocol. I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process. I know the root complex sets the BAR registers of every end…
Joseph Star
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What limits the number of buses, devices and functions on a PCI bus?

I am learning the PCI/PCIe bus. I learned that: A PCI hierarchy can support at most 256 buses. A PCI bus can support at most 32 devices. A PCI device can have at most 8 functions. I checked the Configuration Header Type 0. There's a Device ID…
smwikipedia
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32 UART on a single system

I need to add 32 serial ports to an SBC, for my tests I'm using a raspberry CM4, but it could also be a similar SBC. I'm trying to figure out what solution is best for having 32 serial ports on my system. From a first analysis I understood that the…
Federico Massimi
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this field simply indicates the number of returned…
EquipDev
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What is "shadow" configuration space?

In a github project I saw a feature as follows: Support for writing to custom shadow configuration space. I know what PCI config space is but what is a "shadow configuration space"? I google'd but could not come across anything that explains it…
Joe Toe
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What is the maximum number of devices a single PCI bus can handle?

During system initilization software enumerates the different buses, devices and functions with the help of two I/O Ports (CONFIG_ADDRESS 0xCF8, CONFIG_DATA 0xCFC) and two configuration cycle types. Type 1 PCI Configuration Cycle Type 0 PCI…
blackdog
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Does PCI require bus transaction routing

Does pci require routing mechanism in those 2 cases The two devices are on the same PCI bus and aren't seperated by a bridge. They aren't on the same PCI bus. I don't think it requires a routing mechanism in first case because pci devices all…
John greg
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Remapping a PCI(e) device when another core is accessing the device

According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)? If not, are traces ("litmus tests") like the following…
Abhishek Anand
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Detect power/run status of PC in hardware

This may well be a daft question and/or a failure to google effectively (and apologies if this would be a better fit on SuperUser or somewhere else?) but is it possible, in low-level hardware, to detect the "run" status (possibly ACPI state) of a…
John U
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What limit the pci-e splitting on this case?

I am trying to understand the PCI-E principles but I miss something. The reason why I need to understand that is because I working on a project that involve a lot of SATA HDD to be connected to one machine. Because the HDDs are heavy and occupy a…
sniper
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Does my PCIe platform support CLKREQ#?

I succeeded entering ASPM L1.1 and L1.2 for my device. After entering ASPM L1.1 or L1.2 and trying to initiate to exit from Host side, I saw some hosts that are: • Able to initiate an exit from ASPM L1.1 and L1.2 using CLKREQ# (Host side is pulling…
Omer G
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PCIE Gen 2 Intra-Pair Skew

I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair: Considering the capacitors the skew is ~50 mills: this is the relevant part of the stack up for my question: the traces are on…
Firas Abd El Gani
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