ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.
Questions tagged [modelsim]
169 questions
10
votes
1 answer
How do I debug red signals in ModelSIM?
I have to design a state machine using only NAND gates for the combinatorial part and D flip flops for the sequential logic. Everything should run at a clock of 1ghz/53.
Now before you assault me with "we'll not do your homework for you", let me…
Azurium
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10
votes
2 answers
Can you interface a Modelsim testbench with an external stimuli
I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I would love to be able to model the interaction…
Cort Ammon
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8
votes
1 answer
Why does this simple VHDL pattern for a shift register not work as expected
At first glance you would expect the VHDL source code below to behave as a shift register. In that q, over time would be
"UUUU0", "UUU00", "UU000", "U0000", "00000", ....
but instead it is always U after five (or more) consecutive clock…
Jay M
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7
votes
1 answer
How do I save a waveform from ModelSim for later opening/viewing
If I save the waveform, it is saved as a .do file in ModelSim/QuestaSim. This does not help as later I will have to run the simulation to get the wave back anyway!
What I am looking for is means by which all the wave (their data at points in time)…
quantum231
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7
votes
1 answer
VHDL Procedure - Same variable for input/output parameter
I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity var_test is
port
(
…
sebi707
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5
votes
1 answer
Simulating an IP core in Modelsim is delayed by one clock cycle
I compiled the IP core library in Modelsim. The library from Xilinx is installed on my computer and I also created a ROM using the Xilinx tools. However when I simulate the IP core I find that fetching data from the ROM will delay the simulation by…
zijuexiansheng
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5
votes
3 answers
How to Add the Xilinx Library to Modelsim?
I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily add the Xilinx library to ModelSim?
EDIT:
A few…
sj755
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4
votes
2 answers
how slow are modelsim free licences?
I know in free licenses of modelsim / questa simulations run slower than the full version.
But how slow? will it be 2x 3x 10x faster in the paid version?
what about actel/microsemi free version ?
Cristian Mardones
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4
votes
2 answers
What is the standard way to represent fixed point numbers in VHDL?
Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be synthesized?
How does one see fixed point…
quantum231
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4
votes
1 answer
Why does Modelsim say that VHDL shared variables must be protected?
So I created a shared variable in a purely non-synthesizeable code.
When compiling ModelSim generates a warning:
(vcom-1236) Shared variables must be of a protected type.
Why is it a warning and not an error if the shared variable must be…
quantum231
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4
votes
5 answers
How to speed up Modelsim simulation
How can I get Modelsim to run faster for simulation rather than
something in the picosecond range (time interval)? Are there any other
methods for speeding up simulation? It takes 45 minutes to get to 1ms as
of now. I want the simulation to run…
Alex Krish
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4
votes
2 answers
ModelSim Error : " could not find interpreter "ScintillaTk" "
I have installed ModelSim 10.4 X64, when I want to open a vhd file in editor an error shown in "Transcript" window as :
" could not find interpreter "ScintillaTk" "
I searched about that and I found out that this problem occurs when ModelSim…
Mahmoud_Mehri
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4
votes
1 answer
VHDL simulation shows 'X' for input
I'm new to VHDL and I'm trying to simulate an array multiplier.(I have used verilog before). However in the simulation results it shows 'X' for inputs which used to be '1'.Here is the result:
And this is the Testbench:
LIBRARY IEEE;
USE…
SMA.D
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4
votes
2 answers
What does delta stands for in ModelSIM?
I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file there are some intermediate valued related to deltas…
VSB
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3
votes
2 answers
Simulation of large RAM
I want to test a video IP core that reads a block of memory and writes to it again. The IP core is using the VFBC. My idea for testing was to write a core that looks like the VFBC, but just uses a simple 32Meg RAM as back-end.
It is allocated like…
Karsten Becker
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