Electrical Engineering Stack Exchange
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Questions tagged [mips]

MIPS is a reduced instruction set computer (RISC) architecture that has both 32 and 64-bit variants. The technology is often licensed as IP cores to manufacturers. The Microchip PIC32 series is an example of a common microcontroller based on the MIPS M4K core and several FPGAs include a MIPS microprocessor.

MIPS is a reduced instruction set computer (RISC) architecture that has both 32 and 64-bit variants. The technology is often licensed as IP cores to manufacturers. The Microchip PIC32 series is an example of a common microcontroller based on the MIPS M4K core and several FPGAs include a MIPS microprocessor.

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Why MIPS uses R0 as "zero" when you could just XOR two registers to produce 0?

I think that I am looking for an answer to a trivia question. I am trying to understand why the MIPS architecture uses an explicit "zero" value in a register when you can achieve the same thing by just XOR'ing any register against itself. One…
b degnan
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How many clock cycles does a RISC/CISC instruction take to execute?

According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following: The single-cycle microarchitecture executes an entire instruction in one cycle. (...) The…
user76520
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How are various functions (eg. add, subtract, and, etc) implemented in ALU?

I am wondering since there are so many functions an ALU need to do, how might I start implementing one (a homework where I am supposed to implement a MIPS system with Logisim, using basic Gates, Flip-flops etc). The part I am confused about is how…
Jiew Meng
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Problems while trying to flash a memory using openocd and jtag

I'm using openocd and jtag for the very first time in my life (after 30 years of playing with electronics), when I dump the flash using dump_image, I got a 4 byte sequence (0x80 0x01 0x59 0x18) in every Kb. downloaded. Example 0x000000 0x80 0x01…
Luis Backup
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MIPS Assembly Memory Addressing "Pseudo Direct Addressing"

Could anyone explain how does Pseudo Direct Addressing work in MIPS? I don't really get how does using the last 4 bits from the PC (Program Counter) fit into the picture? Suppose I want to goto Address 0000 0000 0000 0000 0000 0000 0000 0100 And…
Jiew Meng
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MIPS (PIC32): branch vs. branch likely

It's been a while since I've looked at the recent Microchip processors & I've been trying to learn a little bit about the PIC32 MIPS instruction set. I noticed there are two sets of branch instructions; the programming guide says this: 4.1.3.2…
Jason S
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Parallel multiplication hardware

This picture is taken from Computer Organization and Design, Fourth Edition, David A. Patterson, John L. Hennessy. Sorry for the low resolution. I cannot get my head around it. I can see why the bits to the right become lsb's in the product…
Panayiotis Karabassis
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Using JTAG to "explore" a board without damaging it?

I have one Amontec JTAGKey2 Generic USB JTAG cable interface. What I am looking for is some explanation of how to "explore" a device of which I don't know all exact details, but for which I have a BSDL file that fits almost. I cannot damage the…
0xC0000022L
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Implementing Bne in MIPS Processor Circuit

I am trying to include BNE instruction in the following circuit without introducing a new control line. I have thought of many possible ways like adding muxes or and gates etc to implement it but after implementation, a problem always occured with…
Alfred
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MIPS: MARS editor not showing correct value for ASCII string?

I'm using the MARS simulator to explore the MIPS cpu. I have a simple assembly program: .data ascii1: .asciiz "8C@2" I expect the value in the memory address for ascii1 to be 0x38434032 (the hex equivalent for the ascii bit pattern for "8C@2"). …
Fred
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Difference between LW and SW in MIPS assembly

One of my homework questions was to find the 3rd element stored in an array in MIPS, here is my code la $t0, array0 # Loads the address of variable array0 into $t0 lw $t1, 12($t0) # Loads the value of the 3rd element of variable array0 using the…
user1873746
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Atomic operations using extended inline assembler of C32

I'm trying to write atomic code, in my example below I need to perform simple operation a ^= 1; static volatile int a = 0; //-- a ^= 1; __asm__ __volatile__( "xori %0, %0, 1" : "=r"(a) : "r"(a) …
Dmitry Frank
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What was the advantage of a 64-bit processor in the N64?

The Nintendo 64 debuted in 1996 and featured a 64-bit MIPS processor. My understanding is that PCs didn't start appearing with 64-bit CPUs until 2003. What was the advantage of using a 64-bit CPU in 1996? Presumably, back then addressing more than…
GabrielF
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5 cycle instruction forwarding - MIPS

Consider the following MIPS instructions: lw r6, 0(r1) lw r5, 0(r2) add r5, r5, r6 Assume I have full forwarding capabilities. I know that when I produce a value, I only "forward" it to another next instruction right before I consume it. With that…
user91567
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Why don’t most RISC ISAs write integer MULH/MUL or DIV/REM to two general-purpose registers?

Most hardware multiplication and division algorithms can compute the high and low words of a product of two integers, or both the quotient and remainder of the division of two integers, at the same time. In major RISC ISAs, there are many different…
Davislor
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