Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [microsemi-fpga]

Use this tag when your question specifically pertains to the Microsemi line of FPGAs and SoC-FPGAs.

Microsemi’s current FPGA and SoC-FPGA product lines include:

  • PolarFire (Mid-Range FPGAs)
  • RTG4 (Radiation-Tolerant FPGAs)
  • IGLOO2 (Low-Density FPGAs)
  • Mi-V RISC-V Ecosystem (Low-Power FPGAs)
  • SmartFusion2 (SoC FPGAs)
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what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and how do we verify this.
srihari
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What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

This question is along the lines of What files/directories are needed to recreate a Xilinx PlanAhead project? but for an Actel/Microsemi FPGA design. I'm looking for a fairly standard design with Verilog and/or VHDL, project files, and a few cores.…
Brian Carlton
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Smartfusion2 Programmer Error

I have recently start using the M2S150 Development kit from Microsemi and have run into an issue when attempting to program the board (via Libero 12.1). When running the "Run PROGRAM Action" command the log reports the following Error: programmer…
EpicFoodCartDestroyer
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How to "Pull Down" LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the LVDS input pair - so my state machine triggers…
Nazar
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Microsemi IGLOO2 FPGA design resources

I want to start working on IGLOO2 FPGA, and I'm new to FPGAs. I searched throughout the internet for tutorials and training courses for Microsemi devices. It has a bad support and resources compared with Altera and other vendors. Can anyone help me…
HochKonik
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate that I can run this at with the FPGA I have,…
gyuunyuu
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Minimum FPGA clock frequency

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020. In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The minimum frequency for the Zynq chip is not…
abunickabhi
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Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown…
nanoeng
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Is there a "universal" JTAG controller peripheral?

JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the JTAG signals as required by the commands inside…
gyuunyuu
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Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual block design: here's what I put in the .sdc…
Nazar
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which interface to use TBI, GMII or MII? (FPGA)

I am working with the SoC FPGA Smartfusion2 M2S010-MKR-KIT. It is intended to exchange some data between the SoC and the PC. For that reason, I aim to use Ethernet. As far as I understood, in order to establish a proper communication using…
Lavender
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Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence of this Flash memory why do we still need the…
Lavender
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Unused bits on a DDR3 chip

I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point-to-point data & fly-by address/command topologies. I'm using ECC with a 16 bit bus, so 18 bits total. Because of that, one of the chips is…
pserra
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RAM1K18 IP - Constant Busy 'z' and Reading "0" on data bus

I am working with an IGLOO2 device and attempting to instantiate a RAM1K18 IP into my design using the SmartDesign Tool in Libero 2023.1. I have a basic testbench in which I establish an address, and attempt to write to it, and read back the data.…
gdagis97
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Giving write enable signal externally by DIP switch to FPGA memory

I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches. Verilog input wire has been declared in the simple memory read write which connects to these DIP switches on an external breakout. The…
abunickabhi
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