Electrical Engineering Stack Exchange
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Questions tagged [microblaze]

MicroBlaze is a CPU implemented in HDL core written by Xilinx for Xilinx FPGAs. It's implementation is optimized for efficient space and execution on their products. It's a full CPU capable of running Linux and other complex operating systems.

MicroBlaze is a CPU implemented in a HDL core written by Xilinx for Xilinx FPGAs. It's implementation is optimized for efficient space and execution on their products. It's a full CPU capable of running Linux and other complex operating systems.

It is supported by Linux's mainstream tree which implies that you don't need any special patches to run Linux on MicroBlaze. GCC also has built-in support for MicroBlaze.

MicroBlaze is seen as the big brother of PacoBlaze.

See also

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Is the Microblaze soft cpu better than the Cortex M3 soft cpu

Is the Microblaze soft cpu better than the Cortex M3 soft cpu in terms of functionality? Given all the buzz about the ARM based processors, I was wondering if to implement an ARM processor on my FPGA or if I should stick to the Microblaze that comes…
user3045
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What are the typical uses for a soft-processor such as MicroBlaze?

I know that the FPGA-DSP combination is typically used for high-end power electronics/ultrasound/MRI/etc. Is it possible for the soft-processor to fully replace the DSP even on lower-end FPGAs such as Spartan 3/6? Added: What would be the reason…
user02222022
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Reset the configuration of FPGA without reprogramming

I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA. I am using JTAG to program the FPGA, which …
Misiker
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Generating a MSS file at command-line?

Is there a way to generate a mss file from the exported SDK XML file at command-line? At the moment, I still have to open xsdk, generate a new hello world project to create the mss file. But I would like to generate the mss file with makefiles.
vermaete
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Designing with AC'97 - why does it not have a (FIFO) buffer?

The AC'97 codec seems to dominate the world of digital audio I/O but, what is weird is that it has neither interrupts nor buffers so that it is difficult to interface with a controller, which has other activities. The AC97 demands polling it…
Val
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Microcontrollers: Can I perform floating point operations in a Microblaze controller?

I wonder if I could perform floating point operations in a Microblaze controller? Thank you to all posible answers with direct references to documentation or articles.
Peterstone
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Relative FPGA Footprint of ARM Cortex M3 vs. MicroBlaze

I may have missed it, but does anyone have experience with the relative resource consumption of a MicroBlaze versus the core for an ARM Cortex M3 IP? It seems like there should be a ballpark comparison of CLBs, BRAMs, and DSP48Es consumed. Thanks.
Daniel Abramovitch
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xiomodule.h no such file or directory

I'm working with MircoBlaze_mcs core and implement simple GIO file from the tutorial but it gives error ( "xiomodule.h" No such file or directory )when I synthesize the project . I find it in the API documentation in the SDK Project Explorer,…
sepeee
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Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to find the Absolute value of an integer which is designated to Verilog core using Xilinx C running on Microblaze, what i have seen is that Verilog treats the negative number as a positive number. I have tried all data types :…
aibk01
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FSL Bus Problem in Xilinx FPGA Data Return

I wrote a custom IP peripheral in Verilog and interfaced it to MicroBlaze, using a hardware co-processor option. I can see the peripheral connected on the System Design Diagram. Everything compiles and the build is successful. Now I can see on…
aibk01
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Problem using FSL with microblaze

I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this. What I did was create a peripheral with one 32b input and one 32b output of the…
toozie21
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How to get MicroBlaze running on Papilio Pro

I am new to the FPGA world, and there seems to be gazzilions of boards and FPGA vendors. I just bought the Papilio Pro, which is based on the Spartan 6 LX9, and although I can already bitstream basic VHDL designs, I was looking to install the…
Hugo Sereno Ferreira
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VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

The following is the top level module of a VC707 based Microblaze/PS2 controller. I have connected a FMC-CE GPIO Daughter Card to the FMC1 Connector on the FPGA and a PMOD-PS2 on the 6 pin GPIO header on the board. What do I need to do to pass…
Vahe
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Vivado Video IPs not working as expected

I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: I have a Video Test Pattern Generator connected…
RN_
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AXI SPI of MicroBlaze connected to SD card

I would like to connect SPI IP core of microblaze on custom board but I have some problem. I need 100-400 KHZ clock but the system clk is 100MHz and SPI Clock is 6.25 MHz. Is it necessary to reduce clk frequency for initialization? I just send CMD0…
Student77
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